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Phase detector for semi-velocity collision type clock data recovery circuit

A technology of phase detector and clock signal, which is applied in the direction of mutually independent oscillating circuits, electrical components, digital transmission systems, etc., and can solve problems such as ripple, output clock frequency or phase jitter

Inactive Publication Date: 2009-08-19
FARADAY TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This undesired surge may cause ripples in the control voltage of the VCO, which in turn may cause frequency or phase jitter of the output clock.

Method used

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  • Phase detector for semi-velocity collision type clock data recovery circuit
  • Phase detector for semi-velocity collision type clock data recovery circuit
  • Phase detector for semi-velocity collision type clock data recovery circuit

Examples

Experimental program
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Embodiment Construction

[0049] Figure 4 It is a block diagram of a phase detector suitable for a half-rate collision clock data recovery circuit according to an embodiment of the present invention. Figure 4 The phase detector includes a sampling device 410 , a comparing device 420 , and an output device 430 , wherein the comparing device 420 is coupled to the sampling device 410 , and the output device 430 is coupled to the comparing device 420 . The sampling device 410 samples the data signal DATA according to the four clock signals CK0 , CK90 , CK180 , and CK270 to provide corresponding four sampled values ​​D0 , D90 , D180 , and D270 . The above four clock signals have the same frequency and different phases, and the phases of the four clock signals differ by 90 degrees, which just divides 360 degrees of a cycle into four equal parts. The comparing device 420 provides four corresponding comparison values ​​UP1 , DN1 , UP2 , and DN2 according to a comparison result between each of the four sampl...

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PUM

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Abstract

The invention relates to a phase detector for a half rate impact clock data recovery circuit. The phase detector comprises a sampling device, a comparison device and an output device. The sampling device samples a data signal respectively according to a plurality of clock signals so as to provide a plurality of corresponding sampling values. The clock signals have the same frequency but different phases. The comparison device is coupled to the sampling device and provides a plurality of corresponding comparison values according to the comparison result between every sampling value and next sampling value in the sampling values. The output device is coupled to the comparison device, responds to the edge triggering of the clock signals and outputs two of the comparison values as a first indicator signal and a second indicator signal. The two indicator signals are the basis for controlling the frequency or the phase of the clock signals.

Description

technical field [0001] The present invention relates to a phase detector (phase detector), and in particular to a phase detection for a half-rate (half-rate) collision type (bang bang) clock data recovery circuit (CDR circuit for short) device. Background technique [0002] Due to the popularization and progress of communication technology, the bit rate of data transmission (bit rate) is getting higher and higher. In very high-speed applications (such as 5GHz), it is a difficult challenge to design an oscillator that is suitable for its adjustment range and under reasonable jitter conditions. Therefore, the half-rate clock data recovery technology is produced, so that the voltage control oscillator (VCO: voltage control oscillator) only needs to generate a clock signal whose frequency is half of the data transmission bit rate, and can track the data signal. [0003] The paper "A 9-16 Gb / s Clock and Data Recovery Circuit with Three-statePhase Detector and Dual-path Loop Arc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/033H03D13/00
Inventor 曾友信熊玟清
Owner FARADAY TECH CORP
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