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Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method

A shallow trench isolation region, inorganic film technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as poor operability, and achieve the effect of enhancing consistency and reducing the possibility of by-products

Active Publication Date: 2011-07-06
SEMICON MFG INT (BEIJING) CORP
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Problems solved by technology

[0007] However, considering the precision required for the vacuum degree of the etching reaction chamber, the operation parameters for pumping to maintain the vacuum degree in the reaction chamber need to be set in advance. If the above method is used to enhance the consistency of the reaction chamber environment, it is necessary to The reaction chamber needs to be improved to achieve precise adjustment of pumping operation parameters, and the operability is poor.

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  • Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method
  • Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method
  • Inorganic film etching method in semiconductor manufacture procedure and shallow groove isolation area forming method

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[0044] As a first embodiment of the present invention, the inorganic film layer includes a polysilicon layer; the operation of etching the inorganic film layer may be an operation of etching the polysilicon gate layer to form a polysilicon gate layer after forming the polysilicon gate layer .

[0045] When the inorganic film layer includes a polysilicon layer, the etching gas includes SiCl 4 , the SiCl 4 The flow range is 10-300sccm, such as 30sccm, 90sccm, 120sccm, 150sccm; when performing the cleaning operation, the reaction power is 500-2000W, such as 1000W, 1250W, 1500W; when performing the cleaning operation, the reaction pressure is 10-2000W 100mT, such as 50mT, 65mT, 80mT; when performing the cleaning operation, the duration of the pre-cleaning operation is 5-20 seconds, such as 10 seconds, 12 seconds, 15 seconds.

[0046] As a second embodiment of the present invention, the inorganic film layer includes a dielectric layer; the dielectric layer includes an oxide layer...

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Abstract

The invention discloses an inorganic film etching method in a semiconductor manufacture procedure, which comprises the following steps: cleaning an etching reaction chamber by etching gases for etching an inorganic film; running a semiconductor substrate provided with the inorganic film and exposing partial mask layer of the inorganic film; and taking the mask layer as a mask, and removing the exposed partial inorganic film by reaction gases containing the etching gases. The method can strengthen the consistency of the environment in the etching reaction chamber and does not need equipment improvement. The invention also discloses a shallow groove isolation area forming method, which comprises the following steps: cleaning an etching reaction chamber by etching gases for forming a shallowgroove; running a semiconductor substrate on which a patterned mask layer is arranged; taking the pattern mask layer as a mask, and etching the semiconductor substrate in partial depth to form the shallow groove; and filling the shallow groove with an isolation layer to form a shallow groove isolation area. The method can strengthen the consistency of the environment in the etching reaction chamber when the shallow groove is formed, and does not need equipment improvement.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for etching an inorganic film layer in a semiconductor manufacturing process and a method for forming a shallow trench isolation region. Background technique [0002] In the semiconductor manufacturing process, it usually involves multi-step etching operations to form patterns in certain inorganic film layers. like figure 1 As shown, the step of performing the etching operation includes, step 101: running the semiconductor substrate having the inorganic film layer and the mask layer exposing part of the inorganic film layer; step 102: using the mask layer as a mask mold, removing the exposed part of the inorganic film layer. Before performing the etching operation, a pre-cleaning operation for removing residues on the inner wall of the etching reaction chamber is also included. The inorganic film layer includes a polysilicon layer, a dielectric lay...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/00H01L21/02H01L21/3065H01L21/308H01L21/311H01L21/3213H01L21/762
Inventor 杜珊珊韩秋华
Owner SEMICON MFG INT (BEIJING) CORP
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