Verification environment system and construction method thereof

A technology for verifying environment and signals, applied in the field of verification, can solve the problems of shortened development cycle, relying on manual editing, lack of unified construction of the main line and automated construction ideas, etc., to achieve the effect of rapid construction

Inactive Publication Date: 2010-01-13
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] 5. There is no unified construction main line and automated construction ideas, and it needs to rely too much on the manual editing of verifiers, but it is more convenient to modify later
With the rapid expansion of the existing chip verification scale, the continuous r

Method used

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  • Verification environment system and construction method thereof
  • Verification environment system and construction method thereof
  • Verification environment system and construction method thereof

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Embodiment Construction

[0029] The embodiment of the present invention provides a method for building a verification environment and a verification environment system. Through the port information at the top layer of the DUT, the construction instructions are transmitted in the direction of the reverse configuration flow, so as to realize the signal-based functional layering and effective reuse of environmental components, and Reduce the gap between design and verification.

[0030] see figure 2 , is a schematic flowchart of the first embodiment of the verification environment building method provided by the embodiment of the present invention.

[0031] In step 100, the top layer of the design under test obtains externally provided port information;

[0032] In step 101, the obtained port information is converted into a port signal that can be recognized by the verification environment;

[0033] In step 102, according to the port signal, a hierarchical structure starting from the top layer of the ...

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Abstract

The embodiment of the invention discloses a verification environment system and a construction method thereof. The construction method of a verification environment comprises the following steps: acquiring port information required by the construction of the verification environment and generating a layered structure of the verification environment; and constructing, layer by layer, parts required by the layered structure of the verification environment in a direction opposite to configured data stream according to port signals from a tested designed top layer. The verification environment system and the construction method thereof can realize effective reuse and fast construction of the verification environment.

Description

technical field [0001] The invention relates to the technical field of verification, in particular to a verification environment system and a construction method thereof. Background technique [0002] Verification is an indispensable process in the chip product development process to prove whether the design function is realized and implemented correctly. In order to better complete the verification, the verification personnel need to often build an appropriate and efficient verification environment around the design. With the rapid development of the field of chip verification in the past 20 years, there are various methods to build the verification environment. At present, it is more commonly used in the industry to build around the simulation top layer, which is to generate a verification environment that just satisfies the design under test (DUT, DesignUnder Test) based on the simulation top layer information, which has the advantages of simplicity and flexibility. [0...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 左细生刘欢方志华
Owner HUAWEI TECH CO LTD
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