Semiconductor memory device

Abstract

A semiconductor memory device includes a plurality of memory cells 205 provided corresponding to nodes of a plurality of word lines (WLBk, WLBk+1) and a plurality of bit line pairs (D1, DB1, D1+1, DB1+1). And column selection lines (S1, S1+1) are provided corresponding to each of the bit line pairs. Each of the memory cell includes an inverter (INV3) receiving power from the column selection line, and having its input connected to the word line and its output connected to gates of access transistors. Only the access transistors of a memory cell whose word line and column selection line are simultaneously selected are turned on.

Description

technical field [0001] The present invention relates to a semiconductor memory device. In particular, it relates to a semiconductor memory device using an SRAM cell. Background technique [0002] In recent semiconductor integrated circuits, the scale of a system mounted on a single-chip semiconductor integrated circuit has increased along with an increase in the degree of integration due to miniaturization, and its operating speed has also tended to increase. Furthermore, in the field of application of semiconductor integrated circuits, the market for mobile devices such as mobile phones, digital cameras, and PDAs is growing rapidly. In such application fields as mobile devices, power saving becomes a great added value of products. In semiconductor integrated circuits for memory, mounting capacity is also increasing year by year, and power saving technology has become a major issue. Especially in SRAM, reduction of charge and discharge current of a bit line (Digit line), ...

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Problems solved by technology

However, the data held by the memory cell 105s that selects the column and selects the word line and the memory cell 105n that selects the column and does not select the word line are different, and the access transistors Tr1n, Tr2n of the non-selected cell 105n and the bit line pair (D, DB) under the situation that is not completely isolated, will be changed to the bit line of low level ( Figure 9 The middle is the data line DB) is kept as high level by non-selection unit 105n, and will be kept as high level bit line ( Figure 9 In the middle, the data line D) is lowered to a low level by the non-selection unit 105n, so a sufficient potential difference is not generated on the bit line pair (D, DB), and there is a case where the sense amplifier 108 cannot read correct data.

[0024] In the writing operation, according to the data written in the write buffer 109, one of the precharged bit line pairs (D, DB) is lowered to a low level, and the other is kept at a precharged high level potential, but the column is selected. And the memory cells 105n of the non-selected word line all keep the data opposite to the write data, and when the access transistors Tr1n, Tr2n and the bit line pair (D, DB) are not completely isolated, the write cache 109 will drop to low power. The flat bit line is raised to a high level, so that the bit line to be kept high by the cache memory 109 is lowered to a low level, so there will be a delay in writing completion time and wrong writing.

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