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Chip package structure

A chip packaging structure and chip technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of the inability to reduce the packaging volume of the chip packaging structure and the long distance spanned by the wires, and achieve the tight design of high-density packaging structures, saving energy Space, the effect of reducing the package volume

Active Publication Date: 2010-03-03
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the design of the power ring and the ground ring, the wires need to span a long distance, and the packaging volume of the chip packaging structure cannot be reduced

Method used

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  • Chip package structure
  • Chip package structure
  • Chip package structure

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Embodiment Construction

[0035] figure 1 It is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. Please refer to figure 1 , a chip packaging structure 10 includes a carrier 100 and at least one chip 110 . The carrier 100 may be a multi-layer board including at least one patterned metal layer disposed on the upper surface of the core layer. In this embodiment, the carrier 100 includes a chip pad 102, at least one ground pad / voltage pad 106, and a plurality of bonding fingers / traces 104 for electrical connection ( figure 1 Only one is shown). The chip 110 is disposed on the die pad 102 and adhered to the die pad 102 by an adhesive 120 . Adhesive 120 can be any suitable film-like adhesive, for example ESP8680-WL of AI Technology Inc., EasyStack of Ablestik Co. TM ATB-225-8 and 5020K. Since the film-like adhesive does not overflow out of the die foot print of the die, the wire bonding fingers or traces 104 can be brought closer to th...

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Abstract

A chip package structure employing a die pad integrated with the ground / voltage pad is provided. The die pad for carrying the chip is split into at least two separate sections for accommodating the ground and the voltage. Due to the design of the die pad, the signal fingers may be extended under the chip to be connected with vias, and thermal / ground vias may be arranged under the die pad for thermal or electrical connections. Through such arrangement, all the fingers are located closer to the die, thus decrease the length of bonding wires and reducing the package dimensions.

Description

technical field [0001] The present invention relates to a chip packaging structure, and in particular to a wire bonding packaging structure. Background technique [0002] Conventional die-attach is liquid and placed in the projected area of ​​the die to secure the die to the die pad. When the chip is pressed into the liquid adhesive, the adhesive overflows to the edge of the chip and sticks to the sidewall of the chip to form a ribbon. The overflowing adhesive may be adsorbed on the pads of the chip, or cover the bond fingers, ground pads or voltage pads located around the chip, thereby affecting the subsequent wire bonding process. [0003] To ensure the success rate of wire bonding, the overflow adhesive can be removed by a plasma process. However, one more plasma process will increase the manufacturing cost of the packaging structure. Alternatively, a solder mask dam can be provided around the die pad to alleviate the adhesive overflow problem. However, this method wi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/13H01L23/488H01L23/48H01L23/367H01L23/58
CPCH01L23/49503H01L2924/01082H01L23/50H01L2224/83101H01L23/49861H01L24/32H01L23/3677H01L2924/01029H01L2224/293H01L2924/01027H01L2224/48091H01L2924/01013H01L2924/014H01L24/49H01L2224/32225H01L2224/32057H01L2224/2929H01L24/48H01L2224/48465H01L2224/83385H01L2224/48247H01L2924/01033H01L2924/01078H01L2224/29198H01L2224/73265H01L2924/3025H01L2224/49H01L2924/00014H01L2924/00H01L2224/45099
Inventor 伯恩·卡尔·厄佩尔特
Owner ADVANCED SEMICON ENG INC
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