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An extended drain transistor and a method of manufacturing the same

A transistor and drain technology, applied in the field of extended drain transistors, can solve problems such as the failure of traditional transistor manufacturing processes, and achieve the effects of reducing hot carrier effects, accurate alignment, and saving silicon area

Inactive Publication Date: 2010-03-31
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, as the dimensions become smaller and smaller, the traditional transistor manufacturing process may fail

Method used

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  • An extended drain transistor and a method of manufacturing the same
  • An extended drain transistor and a method of manufacturing the same
  • An extended drain transistor and a method of manufacturing the same

Examples

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Embodiment Construction

[0061] The examples in the figures are schematic. In different figures, similar or identical components are provided with the same reference numerals.

[0062] In the following, refer to figure 1 , the EDMOS transistor 100 according to an exemplary embodiment of the present invention will be described.

[0063] The EDMOS transistor 100 is monolithically integrated in a silicon substrate 101 . The silicon substrate 101 may be essentially free of any dopants, or may be intrinsically doped so that a channel region 102 is formed in its central portion.

[0064] The EDMOS transistor 100 also includes a polysilicon gate 103 formed on the silicon substrate 101 , wherein the gate 103 has a first vertical sidewall 104 and a second vertical sidewall 105 opposite the first sidewall 104 . The EDMOS transistor 100 comprises an extended drain region 106 implanted as a region of low dopant concentration on the surface portion of the silicon substrate 101 directly adjacent to the second s...

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PUM

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Abstract

An extended drain transistor (100) comprising a substrate (101), a gate (103) formed on the substrate (100), the gate(103) having a first side wall (104) and a second side wall (105) opposing the first side wall (104), an extended drain (106) implanted in a surface portion of the substrate (101) adjacent the second side wall (105) of the gate (103), a spacer (107) on the second side wall (105) ofthe gate (103), a source (108) implanted in a surface portion of the substrate (101) adjacent the first side wall (104) of the gate (103), and a drain (109) implanted in a surface portion of the substrate (101) adjacent the spacer (107) in such a manner that the extended drain (106) is arranged between the gate (103) and the drain (109).

Description

technical field [0001] The present invention relates to extended drain transistors. [0002] Furthermore, the invention also relates to a method of fabricating an extended drain transistor. [0003] In addition to this, the invention also relates to RF circuits. Background technique [0004] In semiconductor technology, efficient fabrication of MOS transistors is key. Especially for RF applications, the need for transistor quality increases. [0005] US Patent 5,828,104 discloses a MOS semiconductor device comprising a MOSFET having an asymmetric LDD structure, having a first heavily doped region on its semiconductor substrate, a lightly doped region formed adjacent to the first heavily doped region, and a second heavily doped region formed away from the first heavily doped region. The first heavily doped region and the lightly doped region serve as the drain region of the MOSFET, while the second heavily doped region acts as the source region of the MOSFET. A multi-par...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/08H01L21/8234
CPCH01L29/66659H01L29/0847H01L21/823418H01L29/6656H01L29/6653H01L21/823468H01L29/7835Y10S257/90
Inventor 菲利皮·默尼耶-贝亚尔安科·黑林格
Owner NXP BV
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