Pulse width signal duty factor detector

Abstract

The invention relates to a pulse width signal duty factor detector which is formed by connecting a current source mirror circuit 1, a capacitor charging and discharging circuit 2, a divider and a rising edge detection circuit 4 of a pulse width signal. In the invention, a mirror constant current source is adopted to respectively charge the two capacitors, the charging voltage peak value during one high-level period and a periodic period of the pulse width signal is obtained on two capacitors and is then divided by the divider to obtain the duty factor to be detected. As the capacitor in the detector is charged and discharged to obtain the charging voltage peak value during the high-level period and the periodic period without filtering the ripple wave, the capacitance is 1000 times less than that of the traditional detector. Besides, the detector does not need stability in the charging and discharging process of the capacitor and can realize real-time detection of the periodic duty factor. The invention breaks the design thought of the traditional duty factor detector and acquires favorable effects of optimizing structure and enhancing the real-time detection function.

Description

technical field [0001] The invention relates to a detector, in particular to a pulse width signal duty ratio detector. Background technique [0002] In the prior art, conventional duty cycle detectors such as Figure 4 As shown, its working process is: when the measured pulse width signal Vi is at a high level, N1 is turned off, P1 is turned on, the capacitor C1 is charged, and the charging circuit is the power supply V DD -PMOS tube P1-resistor R1-capacitor C1; when the input of the measured pulse width signal Vi is low level, N1 is turned on, P1 is turned off, the capacitor C1 is discharged, and the discharge path is capacitor C1-resistor R1-NMOS tube N1-ground . If the duty cycle of the detected pulse width signal Vi is fixed, and the charging and discharging time constants of R1 and C1 are much larger than the switching period, the voltage on the capacitor remains unchanged, then the output voltage V O It can represent the size of the input square wave duty cycle, whic...

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Problems solved by technology

[0010] The main problem of this traditional detector is: the capacitor C1 in the circuit is a filter capacitor, which is responsible for eliminating the output voltage ripple. Therefore, it requires a large capacitor, and its value is calculated as follows:

It can be seen from this that under an allowable ripple, the capacitance value of the circuit is very large. The larger the capacitance, the larger its volume. In this example, the volume of the 10nF capacitor cannot be integrated in the detector, which means The integration level of the detector is greatly reduced, and the detector needs to provide an additional pin for external capacitance, which increases the size of the detector and loose structure

[0018] According to the above calculation, it can also be seen that the detector can only detect the duty ratio after charging and discharging into a steady state. If we need to perform real-time detection of the cycle-by-cycle duty ratio of the measured pulse width signal, The detector is not applicable, which is another disadvantage of it

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