Pulse Width Signal Duty Cycle Detector

Abstract

The invention is a pulse width signal duty cycle detector. It is composed of a current source mirror circuit 1, a capacitor charging and discharging circuit 2, a divider 3, and a rising edge detection circuit 4 of a pulse width signal. It uses a mirror constant current source to charge two capacitors respectively, and obtains the peak value of the charging voltage during the high level period of the pulse width signal and one cycle period on the two capacitors, and then divides it with a divider to obtain the measured duty Compare. Since the charging and discharging of the capacitor in this detector is to obtain the peak value of the charging voltage during the high-level period of the pulse width signal and a cycle period respectively, and does not take on the task of filtering out the ripple, the capacitance is 1000 times smaller than that of the traditional detector, and at the same time , the detector does not need to wait for the stability of the capacitor charging and discharging process, and can realize real-time detection of cycle-by-cycle duty ratio. The invention breaks the design idea of ​​the traditional duty cycle detector, and achieves good effects of optimizing the structure and increasing the real-time detection function.

Description

technical field [0001] The invention relates to a detector, in particular to a pulse width signal duty cycle detector. Background technique [0002] In the prior art, conventional duty cycle detectors such as Figure 4 As shown, its working process is: when the measured pulse width signal Vi is high level, N1 is turned off, P1 is turned on, capacitor C1 is charged, and the charging circuit is the power supply V DD -PMOS tube P1-resistor R1-capacitor C1; when the measured pulse width signal Vi input is low level, N1 is turned on, P1 is turned off, capacitor C1 is discharged, and the discharge path is capacitor C1-resistor R1-NMOS tube N1-ground . If the duty cycle of the detected pulse width signal Vi is fixed, and the time constant of charging and discharging of R1 and C1 is much longer than the switching period, the voltage on the capacitor remains unchanged, and the output voltage V 0 It can represent the size of the input square wave duty cycle, and its calculation is a...

AI Technical Summary

Problems solved by technology

[0010] The main problem of this traditional detector is: the capacitor C1 in the circuit is a filter capacitor, which is responsible for eliminating the output voltage ripple. Therefore, it requires a large capacitor, and its value is calculated as follows:

[0018] According to the above calculation, it can also be seen that the detector can only detect the duty ratio after charging and discharging into a steady state. If we need to perform real-time detection of the cycle-by-cycle duty ratio of the measured pulse width signal, The detector is not applicable, which is another disadvantage of it

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