A Method for Estimating Irradiation Displacement Damage of CMOS Devices

A displacement damage and device technology, applied in semiconductor/solid-state device manufacturing, instrumentation, computing, etc., can solve problems such as changes affecting threshold voltage, inaccurate methods, and device parameter mismatches
CN101763446BInactive Publication Date: 2012-02-01SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
Publication Date
2012-02-01
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention provides a method for estimating radiation displacement damage of CMOS devices, and belongs to the technical field of radiation displacement damage of CMOS devices. The method includes: according to the incident particles hitting three different positions of the source and drain terminals, the channel region and the isolation region of the device, a calculation formula is established: Ids=prob1×case1+prob2×case2+prob3×case3, where case is the incident particle The displacement damage hitting different positions of the device causes the current change of the drain terminal of the device. Prob is the probability that the incident particle hits different positions of the device. According to this calculation formula, the change amount Ids of the device drain current caused by the displacement damage of the incident particle is obtained, so as to estimate Displacement damage of CMOS devices in radiation environment. The invention can accurately estimate the displacement damage effect of devices and integrated circuits in the radiation environment.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to radiation displacement damage of CMOS devices, in particular to a method for estimating the influence of displacement damage effects on the electrical characteristics of CMOS devices. Background technique

[0002] CMOS integrated circuits have followed Moore's Law for decades. The level of integration continues to increase through shrinking device dimensions. As device feature sizes shrink, device performance continues to evolve. However, the reduction in device feature size also brings various downsizing effects and reliability issues. Small size effects mainly include severe degradation of subthreshold characteristics, DIBL (drain-induced barrier reduction), and threshold voltage is very seriously related to channel length; reliability problems mainly include hot carrier effects, oxide layer over time Breakdown (TDDB) and degeneration of PN junction, etc. In order to make deep submicron devices work properly, various impr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More