A Method for Estimating Irradiation Displacement Damage of CMOS Devices

A displacement damage and device technology, applied in semiconductor/solid-state device manufacturing, instrumentation, computing, etc., can solve problems such as changes affecting threshold voltage, inaccurate methods, and device parameter mismatches

Inactive Publication Date: 2012-02-01
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Abstract
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  • Application Information

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Problems solved by technology

Many circuits such as SRAM cells, sensitive amplifiers, and some digital and analog circuits require symmetry of device parameters, and the change of impurity concentration caused by irradiation will affect the change of threshold voltage and make the device parameters mismatch, thus seriously affecting the performance of the circuit.
[0004] Therefore, with the improvement of circuit integration, the method used to predict the single event effect of devices and integrated circuits is no longer accurate. Cannot meet the application of current irradiation technology

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  • A Method for Estimating Irradiation Displacement Damage of CMOS Devices
  • A Method for Estimating Irradiation Displacement Damage of CMOS Devices
  • A Method for Estimating Irradiation Displacement Damage of CMOS Devices

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Embodiment Construction

[0020] The preferred embodiment of the present invention is described in more detail below with reference to the accompanying drawings of the present invention.

[0021] The present invention utilizes the method of Monte Carlo to randomly generate incident particles according to the Gaussian distribution, hits three different positions of device source and drain end, channel region and isolation region according to the incident particles, establishes a calculation formula: I ds =prob1×case1+prob2×case2+prob3×case3, to estimate the displacement damage of the CMOS device in the radiation environment. The specific estimation steps are as follows:

[0022] 1. When a single particle hits the source and drain of a CMOS device, the parasitic resistance of the source and drain increases. With the shortening of the channel length of the MOS transistor, the intrinsic resistance of the channel decreases, while the parasitic resistance of the source and drain regions will not be scaled d...

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Abstract

The invention provides a method for estimating radiation displacement damage of CMOS devices, and belongs to the technical field of radiation displacement damage of CMOS devices. The method includes: according to the incident particles hitting three different positions of the source and drain terminals, the channel region and the isolation region of the device, a calculation formula is established: Ids=prob1×case1+prob2×case2+prob3×case3, where case is the incident particle The displacement damage hitting different positions of the device causes the current change of the drain terminal of the device. Prob is the probability that the incident particle hits different positions of the device. According to this calculation formula, the change amount Ids of the device drain current caused by the displacement damage of the incident particle is obtained, so as to estimate Displacement damage of CMOS devices in radiation environment. The invention can accurately estimate the displacement damage effect of devices and integrated circuits in the radiation environment.

Description

technical field [0001] The invention relates to radiation displacement damage of CMOS devices, in particular to a method for estimating the influence of displacement damage effects on the electrical characteristics of CMOS devices. Background technique [0002] CMOS integrated circuits have followed Moore's Law for decades. The level of integration continues to increase through shrinking device dimensions. As device feature sizes shrink, device performance continues to evolve. However, the reduction in device feature size also brings various downsizing effects and reliability issues. Small size effects mainly include severe degradation of subthreshold characteristics, DIBL (drain-induced barrier reduction), and threshold voltage is very seriously related to channel length; reliability problems mainly include hot carrier effects, oxide layer over time Breakdown (TDDB) and degeneration of PN junction, etc. In order to make deep submicron devices work properly, various impr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50H01L21/8238
Inventor 薛守斌王思浩黄如张兴
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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