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Image encryption and decryption system and method based on FPGA platform and evolutionary hardware

An evolutionary hardware, encryption and decryption technology, applied in the field of information encryption and decryption, can solve the problems of poor flexibility and achieve the effects of fast encryption speed, enlarged key space, and enhanced security

Inactive Publication Date: 2011-12-28
WUHAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But not all rules can be used as keys. The traditional design method separates key design and encryption, and a set of key sets must be designed in advance, which has poor flexibility.

Method used

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  • Image encryption and decryption system and method based on FPGA platform and evolutionary hardware
  • Image encryption and decryption system and method based on FPGA platform and evolutionary hardware
  • Image encryption and decryption system and method based on FPGA platform and evolutionary hardware

Examples

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Embodiment Construction

[0044] The present invention is described in detail below in conjunction with accompanying drawing and embodiment:

[0045] This example is implemented on the XC2VP30 FPGA development board, using PowerPC as the processor, using the on-chip memory BRAM (128KB capacity in the embodiment) and the off-chip memory DDR SDRAM (512MB capacity in the embodiment) as the memory, and using the CF card as the non-volatile memory The volatile memory stores image data. The image data before and after encryption and decryption are all stored in the CF card. Due to the limited on-chip memory BRAM of the FPGA platform, a 512MB memory stick DDRSDRAM can be added to store the stack of software projects.

[0046] figure 1 Shown is the overall structure diagram of the system, because PowerPC is used as the processor, the system has two buses, PLB (Processor Local Bus, processor local bus) and OPB (On-Chip Peripheral Bus, on-chip peripheral bus). The OPB bus connects some low-speed and low-perfo...

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Abstract

The invention relates to an image encryption and decryption system and method based on FPGA platform and evolution hardware. The system is equipped with: configurable embryonic circuit IP core implemented in FPGA, cellular automata image encryption IP core, cellular automaton image decryption IP core Core, function selection IP core, and genetic algorithm module and central control module. Encryption includes steps: evolve the configurable embryonic circuit through genetic algorithm, configure the configurable embryonic circuit IP core with the evolved configuration string, segment the image data, and use the cellular automaton image encryption IP core to encrypt by segment. The decryption includes steps: first configure the configurable embryonic circuit IP core with the configuration string, then segment the information, and use the cellular automaton image decryption IP core to decrypt according to the segment. The system of the invention randomly and automatically generates keys, has a wide range of keys, and effectively realizes key dispersion, thereby improving system security.

Description

technical field [0001] The invention relates to the technical field of information encryption and decryption, in particular to an image encryption and decryption method based on an FPGA platform and evolutionary hardware. Background technique [0002] Evolvable hardware (Evolvable Hardware, EHW) is a hardware circuit that can dynamically change its own structure and behavior through interaction with the environment. It has the ability of self-organization, self-adaptation and self-repair, and can adapt to different environmental requirements and improve its own performance. The general solution process of evolutionary hardware is: first use the evolutionary algorithm to evolve the configuration string of the hardware circuit, then find out the configuration string that meets the requirements, and then use the configuration string to configure the hardware circuit. The main application areas of evolutionary hardware are: automatic design of simple circuits, solving difficult...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N21/2347
Inventor 王峰李元香王珑刘海峰危明
Owner WUHAN UNIV