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Low-complexity and extensible fault-tolerant routing algorithm specific to network on chip

A low-complexity, network-on-chip technology, applied in data exchange networks, error prevention, digital transmission systems, etc., to achieve good scalability, overcome large area overhead, and ultra-low hardware complexity

Inactive Publication Date: 2010-09-15
FUDAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to propose a fault-tolerant routing algorithm with ultra-low complexity, excellent scalability and strong reconfigurability for the Network-on-Chip of the Mesh topology. The hardware overhead can be kept constant and does not change with the system With the expansion of the scale, when the new node fails, the system can still work normally after simple reconfiguration, and its hardware complexity can be made smaller than the traditional fault-tolerant routing algorithm

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  • Low-complexity and extensible fault-tolerant routing algorithm specific to network on chip
  • Low-complexity and extensible fault-tolerant routing algorithm specific to network on chip
  • Low-complexity and extensible fault-tolerant routing algorithm specific to network on chip

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Embodiment Construction

[0044] When the error node occurs in the four corner areas or the four border areas or any single area in the center area, the algorithm can use the above three-step strategy to divide and conquer each one. The error situation in the southern border area is as follows: image 3 As shown in , when a node in the corner area or central area is wrong, we can adopt a similar method to achieve the purpose of bypassing the wrong node to ensure the communication between normal node pairs.

[0045] In order to simplify the configuration of the system, the algorithm can adopt the method of merging and absorbing. In general, two principles are grasped, and the adjacent scattered error nodes are absorbed as much as possible to form a rectangular fault area and approach the corner area as much as possible. , the specific implementation is as Figure 4 shown.

[0046] When the area formed after merging and absorbing wrong nodes spans several different areas, the routers on both sides of th...

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Abstract

The invention belongs to the field of reliable computing technologies and particularly relates to a low-complexity and extensible fault-tolerant routing algorithm for a network on chip. The routing algorithm adopts strategies of system partition and divide-and-conquer, and can better tolerate faults occurred in different parts of a central zone, four boundaries and four corner parts. Under the circumstance of certain nodes fault, the entire system can still work, thereby the fault-tolerant capability and the continuous service capability of the system are greatly enhanced, the yield of chips and the service life of the system are improved in a disguised form, and the cost of the system is reduced. The routing algorithm is applicable to occasions having extremely high requirement on reliability, such as aerospace, military network, financial transactions, banks and other key fields as well as the fields, such as civilian use, consumer electronics, and the like.

Description

technical field [0001] The invention belongs to the technical field of reliability calculation, and in particular relates to a low-complexity and scalable high-performance fault-tolerant routing algorithm for a network on chip of a Mesh topology. Background technique [0002] With the "power wall" (power wall) limiting the performance of single-core processors, computing system design is gradually transitioning to the field of multi-core (Multicore), many-core (Many-core) and even on-chip network. Although so far, the number of cores of commercial processors is relatively small, but in the foreseeable future, the number of cores will follow the "New Moore's Law", doubling each generation on the original basis. Some representative works such as Tilera64 (64 cores), Intel's Teraflop (80 cores), and the 167-core computing platform of the University of California, Davis. [0003] Fault-tolerant design is traditionally only used in fields with particularly high stability require...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56H04L1/00H04L12/721
Inventor 石泽文虞志益曾晓洋陈秀平惠志达杨金达
Owner FUDAN UNIV
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