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Method for realizing decoding, software decoder and decoding device

An implementation method and technology of a hardware decoder, applied in the field of software decoders and decoding equipment, can solve the problems of disadvantageous decoding efficiency, waiting for hardware decoders, waiting for software decoders, etc., and achieve the effect of improving decoding efficiency and realizing parallel processing.

Inactive Publication Date: 2010-09-22
李晶晶
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] During the research and practice of the prior art, the inventors of the present invention have found that the software decoder and the hardware decoder have not been completely parallel in the prior art, and when the decoding time of the software decoder is less than the decoding time of the hardware decoder, There will be a situation where the software decoder waits for the hardware decoder. On the contrary, when the decoding time of the hardware decoder is shorter than the decoding time of the software decoder, the hardware decoder will wait for the software decoder, which is not conducive to improving the decoding efficiency.

Method used

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  • Method for realizing decoding, software decoder and decoding device
  • Method for realizing decoding, software decoder and decoding device
  • Method for realizing decoding, software decoder and decoding device

Examples

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Embodiment 1

[0029] This embodiment will be described from the perspective of a software decoder. The software decoder is used to implement functions such as software decoding and software driving the hardware decoder, while the hardware decoder implements the hardware decoding function.

[0030] A decoding implementation method, such as figure 1 As shown, the specific process can be as follows:

[0031] 101. Perform primary processing on the acquired coded image frame; the primary processing specifically includes: performing software decoding on the acquired encoded image, using a virtual frame memory to simulate a DPB operation after hardware decoding, and obtaining a result of the DPB operation.

[0032] For example, in order to make the division of labor between software decoding and hardware decoding more reasonable, the slice header (slice header) that requires a lot of logical operations can be handed over to the software decoder for decoding, and the data-intensive slice data (sli...

Embodiment 2

[0051] According to the method described in the first embodiment, this embodiment will take the software decoder to parse the slice header, the hardware decoder to decode the slice data, and the code stream to be an H.264 code stream as an example for further description.

[0052] After parsing the slice header, the software decoder generates a decoded message, then buffers the slice data into the decoded message, uses the virtual frame memory to simulate the DPB operation after a frame ends, and caches the result of the DPB operation in the decoded message. Before starting the hardware decoder to decode each frame of encoded image, the software decoder applies for the actual frame memory according to the decoding message, and updates the virtual frame memory mapping table that records the mapping relationship between the virtual frame memory and the actual frame memory, and then Configure and start the hardware decoder with data and virtual frame memory mapping table to perfor...

Embodiment 3

[0070] According to the method described in the second embodiment, a specific example will be used to describe in detail below.

[0071] see Figure 3a , Figure 3a is a schematic diagram of the code stream. Generally, in the code stream, the image of the next frame refers to the image of the previous frame, and the number of reference frames is 1. For example, Figure 3a Include three frames of images: 1, 2 and 3, then 1 has no reference frame, 1 is the reference frame of 2, 2 is the reference frame of 3, and so on if there are other frames later.

[0072] In this embodiment, the recording of the mapping relationship between the virtual frame memory and the actual frame memory in the virtual frame memory mapping table is taken as an example for description. Wherein, the structure of the virtual frame memory mapping table may be specifically shown in Table 1;

[0073] Table I:

[0074] VFB

RFB

Remark

0

Actual frame memory information (address,...

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Abstract

The invention discloses a method for realizing decoding, a software decoder and a decoding device. When used for decoding an encoded image, the software decoder of the embodiment of the invention adopts virtual frame storage to imitate DPB operation of a hardware decoder after decoding the encoded image of a frame to ensure that the encoded image of the next frame can be decoded without waiting the finish of the decoding of the hardware decoder so as to avoid the situations that the software decoder and the hardware decoder wait for each other because the DPB operation is performed only after the finish of the decoding of the hardware decoder in the prior art. The method, the software decoder and the decoding device can well realize parallel processing of the software decoder and the hardware decoder, and improve the decoding efficiency.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a decoding implementation method, a software decoder and a decoding device. Background technique [0002] With the continuous increase of communication bandwidth, people's demand for communication is also constantly enriched. After voice, video transmission has become a new bright spot in the field of communication. In order to make video transmission easier, video compression technology also appears. H.264 is one of a kind. After the compressed video arrives at the terminal, it needs to be decoded before it can be played. In order to improve the decoding speed, the H.264 decoder architecture of the embedded central processing unit (CPU, Central Processing Unit) combined with the dedicated decoding acceleration unit is generally used at present. Decoding, wherein the acceleration unit is generally Digital Signal Processing (DSP, Digital Signal Processing) or Application S...

Claims

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Application Information

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IPC IPC(8): H04N7/26H04N19/44
Inventor 曹国栋闫智伟顾骧
Owner 李晶晶
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