Wafer defect marking system

Abstract

The invention provides a wafer defect marking system, which comprises a bearing platform, a micro observation module, a reading module, a first operation module, a second operation module, an image display module, an image conversion module, an alignment module and a chip defect marking module. The wafer defect marking system can be provided for an operator to directly perform marking work of a defected chip on the image display module.

Description

technical field [0001] The invention relates to a wafer defect marking system, in particular to a wafer defect marking system applied in semiconductor wafer detection. Background technique [0002] In the semiconductor wafer manufacturing process, in addition to using electrical tests to test the good and bad of the die on the wafer before the wafer is cut, it is also necessary to ask the operator to visually inspect the appearance of the die on the wafer. To ensure that the surface of the chip is free from scratches, dirt... and other defects. Usually, the operator visually inspects the chips on the wafer with a microscope, and after observing the abnormal chip with defects, finds out the corresponding position of the abnormal chip on a paper wafer map and marks it according to the position of the abnormal chip. After marking the abnormal chips of a wafer on the paper wafer map, it is necessary to delete them one by one according to the position of the abnormal chips on th...

AI Technical Summary

Problems solved by technology

After marking the abnormal chips of a wafer on the paper wafer map, it is necessary to delete them one by one according to the position of the abnormal chips on the paper wafer map. However, when the number of abnormal chips on the paper wafer map increases more, it will take longer for the operator to remove abnormal chips

[0003] Therefore, based on the above, when the operator visually marks the abnormal chip on the paper wafer map, it is prone to artificially unclear or wrong marking, resulting in the generation of bad wafer map.

Moreover, as the size of chips is becoming thinner and smaller today, it is even more difficult for operators to find the corresponding position on the paper wafer map for marking, which will result in time-consuming and labor-consuming operations and increase the error rate

Finally, after the paper wafer map is completed, it needs to be manually counted in the counting system again, and this step needs to spend time and cost again

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