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Multicore microprocessor and debug method thereof

A core microprocessor and microprocessor technology, applied in the field of multi-core processors, can solve the problems that nuclear interaction errors cannot be copied, and cannot be coordinated

Active Publication Date: 2012-11-21
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Furthermore, errors related to some nuclear interactions are likely to be unreproducible due to uncoordinated procedures such as stop and restart of the tracker

Method used

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  • Multicore microprocessor and debug method thereof

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Embodiment

[0021] To address the above problems, a dual-core processor can be modified such that when one core's tracker triggers, it can interrupt the other processor to cause the tracker in the other processor to send a state checkpoint. Then, the two cores can communicate with each other, so that both cores can be restarted at the same time.

[0022] refer to figure 1 , figure 1 is a circuit diagram showing a system 100 with a dual-core processor 108 according to an embodiment of the present invention. System 100 includes chipset 128 , wherein chipset 128 is coupled to dual-core processor 108 via processor bus 134 . System 100 also includes system memory 132 coupled to chipset 128 . Dual-core processor 108 includes two cores, which may be individually referred to as Core 0 104A and Core 1 104B or may be collectively referred to as Core 104 . Core 0 104A writes its state 158A to system memory 132 , and core 1104B writes its state 158B to system memory 132 , wherein the state 158A o...

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Abstract

A multicore microprocessor and a debug method thereof. The multicore microprocessor includes a first processing nuclear, a second processing nuclear and a bus coupled to the first and second processing nucleus. The bus transmits messages between the first and second processing nucleus. Responding to a detected given event, the first processing nuclear stops executing user program instruction and interrupts the second processing nuclear through the bus. Responding to the interruption of the first processing nuclear, the second processing nuclear stops executing user program instruction. Each processing nuclear outputs its state after stopping executing user program instruction. Each processing nuclear waits until receives a notification from the other processing nuclear through the bus to start to extract and execute user program instruction, wherein the notification is given off when the other processing nuclear prepares to extract and execute the user program instruction. The double nucleus are capable of transmitting state detection points to a memory at an identical time and simultaneously recovering to execute the user program instruction.

Description

technical field [0001] The present invention relates to multi-core processors, in particular to the debugging of multi-core processors. Background technique [0002] The processor includes a set of microcode routines, which are in a dormant state (dormant) until activated by software to write into the control register (eg WRMSR instruction). The microcode program is hereinafter referred to as a tracer, which can be used as a tool for debugging and performance tuning of the processor. Once the tracker is started, various events can trigger the tracker to collect processor status information and write the processor status information to a specified address in the memory. One of the ways to use a tracker is to invoke the tracker at regular intervals. For example, every time the processor executes and retires N instructions (eg, 100,000 instructions, the number of which is set by the user), the tracker dumps the state of the processor to the memory. The transferred processor ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/18
Inventor G·葛兰·亨利陈巨轩
Owner VIA TECH INC