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Sharing bandwidth of a single port sram between at least one dma peripheral and a cpu operating with a quadrature clock

A technology for central processing units and peripheral devices, applied in electrical digital data processing, instruments, etc., can solve the problems of large die area, expensive dual-port SRAM, etc.

Active Publication Date: 2013-07-31
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Dual-port SRAMs are more expensive and occupy a larger die area than the more common single-port SRAMs

Method used

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  • Sharing bandwidth of a single port sram between at least one dma peripheral and a cpu operating with a quadrature clock
  • Sharing bandwidth of a single port sram between at least one dma peripheral and a cpu operating with a quadrature clock
  • Sharing bandwidth of a single port sram between at least one dma peripheral and a cpu operating with a quadrature clock

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Embodiment Construction

[0013] Reference is now made to the drawings, which schematically illustrate details of the example embodiments. In the drawings, the same elements will be represented by the same numerals, and similar elements will be represented by the same numerals with different lowercase letter suffixes.

[0014] Referring to FIG. 1 , which is a schematic block diagram of a prior art dual port static random access memory (SRAM) coupled to a central processing unit (CPU) and direct memory access (DMA) peripherals. Dual port SRAM 102 has two read / write interfaces 104a and 104b. A read / write interface 104a is coupled to CPU 108 via memory bus 106 . Another read / write interface 104b is coupled to a DMA peripheral 112 through a memory bus 110 . Having two read / write interfaces 104 allows CPU 108 and DMA peripheral 112 to access dual port SRAM 102 without having to undergo memory bus arbitration. However, dual port SRAM 102 is more expensive and requires more die area than single port RAM. ...

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Abstract

A dual or triple access interface (e.g., hardware and software implementation) allows a CPU and at least one DMA peripheral, e.g., Universal Serial Bus (USB) DMA engine, to transfer data in and / or out of a common single port SRAM by negotiating access requests between the CPU and the DMA peripheral, and then subsequently forms memory cycles to the single port SRAM to satisfy both the CPU's and DMA peripheral's memory access throughput requirements. This allows the CPU and the at least one DMA peripheral to access a shared single port SRAM by time multiplexing granted accesses between, for example, two or three simultaneous memory access requests, thus eliminating the need for a dual port memory.

Description

technical field [0001] The present invention relates to digital devices and their memory access, and more particularly, to a shared single-port static random The way to access the bandwidth of the memory (SRAM). Background technique [0002] The CPU and high-speed DMA peripheral can share memory by coupling to a dual-port SRAM to allow the CPU and DMA peripheral to proceed without any type of memory bus arbitration between the CPU and DMA peripheral during their respective memory accesses independent access. Dual-port SRAMs are more expensive and occupy a larger die area than the more common single-port SRAMs. Contents of the invention [0003] What is needed is a way to share the bandwidth of a single-ported SRAM between a CPU operating on quadrature clocks and a DMA peripheral. In accordance with the teachings of the present invention, a dual access interface (e.g., hardware and software implementation) will allow a CPU and a DMA peripheral (e.g., a Universal Serial B...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16
CPCG06F13/1663
Inventor 杨·元杨斯戈尔伊戈尔·沃耶沃达
Owner MICROCHIP TECH INC