Pixel array structure

Abstract

The invention discloses a pixel array structure, which comprises a conductive hole, a first metal layer, a transparent conductive layer and a second metal layer, wherein the conductive hole is electrically connected to a common voltage of a pixel; the first metal layer is electrically connected to the common voltage of the pixel; the transparent conductive layer conducts the common voltage to another pixel next to the pixel, so that the common voltage is used as the common voltage of the another pixel; and the second metal layer is arranged between the first metal layer and the conductive hole to reduce the distance between the conductive hole and the gate line of the pixel, so that the opening ratio of the pixel is increased. When the pixel array structure is used, a virtual electrode is arranged between the metal layer and the conductive hole to reduce the distance between the conductive hole and the gate line of the pixel, so the loss caused by a netty common voltage structure to the opening ratio of the pixel is reduced. In addition, the virtual electrode can avoid micro-conduction of the conductive hole between the gate line and the common voltage when displacement or specification is changed.

Description

technical field [0001] The invention relates to the structural design of a liquid crystal panel, in particular to the design technology of the pixel array structure of the liquid crystal panel. Background technique [0002] In a conventional active matrix liquid crystal display, each pixel has a thin film transistor whose gate is connected to a horizontal scanning line, whose source is connected to a vertical data line, and whose drain is connected to a pixel electrode. For a pixel array structure containing many pixels, on the same scanning line in the horizontal direction, the gates of all thin film transistors are connected together, so the applied voltage is linked, for example, on a certain scanning line When a sufficiently large positive voltage is applied, all thin film transistors on this scanning line will be turned on, and the pixel electrodes on this scanning line will also be electrically connected to the data line in the vertical direction, and the corresponding...

AI Technical Summary

Problems solved by technology

However, since the positioning of the via hole must consider the line width and overlap of the photoresist coating process, exposure process, and development process, the specific position of the via hole will cause a serious loss to the pixel aperture ratio, thereby affecting the transmittance. and increased backlight loss

In addition, the distance between the via hole and the gate line of the pixel should not be too close, so as to avoid false conduction between the common voltage and the gate line.

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