Test method and system of multiple paths of E1 ports for realizing STM-1 interface

A technology of STM-1, test method, applied in transmission systems, digital transmission systems, electrical components, etc.

Inactive Publication Date: 2011-03-30
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Another object of the present invention is to provide a kind of test system that realizes the multi-channel E1 mouth of STM-1 interface, is used to solve the problem that multi-channel E1 mouth tests simultaneously on the STM-1 interface

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  • Test method and system of multiple paths of E1 ports for realizing STM-1 interface
  • Test method and system of multiple paths of E1 ports for realizing STM-1 interface
  • Test method and system of multiple paths of E1 ports for realizing STM-1 interface

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Embodiment Construction

[0030] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0031] figure 1 Shows the flow chart of the multi-channel E1 port test method of the STM-1 interface provided by the present invention, such as figure 1 Shown:

[0032] Step S101: Establish a one-to-one correspondence between each E1 port on the STM-1 interface on the line side of the intermediate device and the N-way E1 port on the branch side of the intermediate device, and each E1 port in the N-way E1 port series test channel passes The STM-1 interface on the line side of the intermediate device establishes a one-to-one correspondence with all E1 ports of the STM-1 interface of the device under test. This one-to-one correspondence is realized through mapping. The...

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Abstract

The invention discloses a test method and system of multiple paths of E1 ports for realizing an STM-1 interface. The method comprises the following steps of: building one-to-one correspondence relationship between each E1 port on the STM-1 interface at the middle equipment circuit side and N paths of E1 ports at the middle equipment branch circuit side; sequentially connecting N paths of E1 ports at the middle equipment branch circuit side in series, forming a serial connection test passage of N paths of E1 ports, connecting an SDH (Synchronous Digital Hierarchy) test instrument, and carrying out butt joint between the STM-1 interface at the middle equipment circuit side with the STM-1 interface of the tested equipment; and simultaneously testing all the E1 ports of the STM-1 interface of the tested equipment by the SDH test instrument through the serial connection test passage of the N paths of E1 ports, wherein N is an integer greater than or equal to 2. The middle equipment is used for completing the serial connection of multiple paths of E1 ports and the mapping of the E1 ports to the STM-1 interface, the monitoring of each path of E1 port of multiple paths of E1 ports on the STM-1 interface through network management is completed, and the simultaneous test of multiple paths of E1 ports on the STM-1 interface is realized.

Description

Technical field [0001] The present invention relates to E1 port testing in channelized STM-1, in particular to a testing method and system for multiple E1 ports realizing STM-1 interface. Background technique [0002] When channelized STM-1 interface is tested, the interface error performance test is generally performed by testing one of the 63 E1 ports of the channelized STM-1 interface. However, due to differences in physical wiring and clock distribution, Each E1 port of the 63 E1 ports of the channelized STM-1 interface has its own characteristics. Testing only one or a few of them does not represent the error performance of all the channels of the 63 E1 ports of the channelized STM-1 interface. It does not mean that all the channels of the 63 E1 ports of the channelized STM-1 interface can send and receive packets normally, so under strict test requirements, the 63 E1 ports of the channelized STM-1 interface should be tested, but because each channel is tested in general exp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/26
CPCH04L43/50H04L12/2697
Inventor 申雅玲
Owner ZTE CORP
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