Multi-core system and implementation method of timer in same
A technology of a multi-core system and an implementation method, which is applied to instruments, signal generation/distribution, computers, etc., can solve problems such as low system performance, improve reliability and stability, and facilitate balanced processing.
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Embodiment 1
[0049] In this embodiment, in order to overcome the lack of a unified and reliable timer implementation mechanism in multi-core system applications, a method for implementing a timer in a multi-core system is provided. The method includes the following steps:
[0050] Step 1, system initialization, each core in the multi-core processing system establishes a corresponding timer processing linked list in the shared memory, and each timer processing linked list corresponds to a corresponding time interval.
[0051] Step 2, create a timer. The core that needs to create a timer first applies for a timer control block, calculates according to the timer intervals corresponding to each core, and divides the timers into combinations of intervals corresponding to each timer linked list.
[0052] Step 3, adding timers, according to the principle of adding the kernel last, adding it to the corresponding timer linked list according to the combination sequence obtained through calculation. ...
Embodiment 2
[0056] Taking the multi-core system including 4 CPUs as an example, the implementation method of the timer in the multi-core system in the embodiment of the present invention is described in detail. Assuming that 4 CPUs respectively correspond to timer linked lists of 1ms, 10ms, 100ms, and 1000ms (that is, timing intervals), CPU1 and CPU3 create a timer respectively, and the duration of the timer is 303ms and 1323ms respectively.
[0057] Figure 4 is a schematic diagram of creating a timer according to the second preferred embodiment of the present invention, such as Figure 4 As shown, the entry of the 303ms timer created by CPU1 and the entry of the 1323ms timer created by CPU3 are first added to queue 0 (that is, the timer processing linked list corresponding to CPU0) for processing according to the processing sequence of the kernel. Because when calculating the adding order of timers, the 303ms timers created by CPU1 correspond to the timer processing queues of CPU0 and ...
Embodiment 3
[0063] Figure 7 It is a flow chart of the implementation method of the timer in the multi-core system according to the third preferred embodiment of the present invention, such as Figure 7 As shown, the method may include the following processing steps:
[0064] Step S702, system initialization, creating a timer processing linked list corresponding to each CPU.
[0065] Step S704, calculate the adding order according to the duration of the timer to be created, and hang it into the corresponding timer processing linked list.
[0066] Step S706, each CPU regularly processes the timer of the corresponding linked list, and adds it to the corresponding timer linked list according to the remaining time of the timer.
[0067] Step S708, each CPU judges whether its timing queue has timed out, that is, each CPU judges whether there is a timeout timer to be processed. If yes, go to step S710, otherwise go to step S706 to continue processing.
[0068] Step S710, judging whether the...
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