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Method for reducing size of territory file

A file size and layout technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of increasing layout file size, lack of communication, and high complexity

Active Publication Date: 2011-05-04
SEMITRONIX
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually, in a large-scale layout file, the shape and size of many polygons on the same layer are exactly the same, but the relative positions in the layout are different; The degree is very high, and usually requires multiple departments to work together, and the department personnel are divided into modules. This design method lacks communication, effective organization and planning, and it is easy to produce more such same-layer shapes and sizes. Polygons with different positions
These same polygons will consume a lot of storage space, greatly increasing the size of the layout file
The larger the layout file will occupy more storage resources, and at the same time, the layout design tool will occupy more computer memory when reading the layout file, which will affect the running speed of the computer and the efficiency of the design tool

Method used

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Embodiment Construction

[0032] The present invention will be described in detail below in conjunction with the embodiments and accompanying drawings, but the present invention is not limited thereto.

[0033] like figure 1 As shown, a method for reducing the size of the layout file includes the following steps:

[0034] (1) read in the original layout file;

[0035] The original layout file stores the layers of all related geometric figures and the basic composition of the geometric figures, and reading the layout file will obtain the layer and basic composition information of all the geometric figures. Usually, there are several layers stored in the original layout file, and there are several polygons on each layer, and each polygon includes the layer to which the polygon belongs and the coordinates of all vertices of the polygon.

[0036] For simplicity, in figure 2 The schematic diagrams of two typical different levels and several polygons on the levels in the original layout file are given in...

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Abstract

The invention discloses a method for reducing the size of a territory file, and provides a method in which quotations of a reference unit are utilized to replace multiple uniform polygons in a territory based on the screening and matching on the uniform polygons in a large-scale territory file in order to reduce the numbers of coordinates needing to be stored in the territory file, thereby reducing the size of the territory file of super-large-scale integration design. By using the method, storage resources occupied by the territory file and a computer memory occupied when a territory design tool reads the territory file are greatly reduced, and the operation speed of a computer and the use efficiency of the territory design tool are improved. The method disclosed by the invention is especially suitable for the super-large-scale integration design.

Description

technical field [0001] The invention relates to the field of computer-aided design of integrated circuits, in particular to a method for reducing the size of layout files used for VLSI design. Background technique [0002] The layout file (also called GDSII file, GDS=Graphic Database System) is a de facto standard used to describe the mask geometry. It is a binary format, and the content includes the basic composition of the layer and the geometry. GDSII is a timing providing format, which fully describes the circuit units distributed in each production layer. Used for data transfer between design tools, computers, and mask manufacturers for semiconductor physical board fabrication. [0003] With the development of integrated circuit design and manufacturing technology, the complexity of integrated circuits is getting higher and higher, and the number of transistors that can be integrated on a chip has even reached tens of millions of gates. The higher the complexity and i...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 张波任杰郑勇军马铁中
Owner SEMITRONIX
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