Method for fabricating a gate structure

Abstract

A method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode. The gate structure of the invention can be etched in the interlayer dielectric layer or the substrate without notches by dry chemistry.

Description

technical field [0001] The present invention relates to integrated circuit fabrication, and more particularly to semiconductor devices with gate structures. Background technique [0002] As the transistor size shrinks, the gate oxide thickness needs to be reduced to maintain performance as the gate length is reduced. However, in order to reduce the gate leakage current, a high-k gate oxide layer is used, which is at the same effective thickness as the general gate oxide used in future technology nodes. It may have a better physical thickness. [0003] In addition, when technology nodes shrink, in some integrated circuit designs, it is necessary to use metal gate electrodes instead of known polysilicon gate electrodes (poly gate electrodes) in order to improve the reduced features. Dimensions of performance of the device. One of the processes for forming the metal gate electrode is the "gate last" process, which allows the metal gate electrode to be prepared in the "last" ...

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Problems solved by technology

Therefore, characteristics such as threshold voltage and reliability will be degraded

On the other hand, these notches 118a appearing in the interlayer dielectric layer 118 may become a metal receiving area in the subsequent process, thereby increasing the possibility of short circuit and / or device failure.

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