Method for making shallow channel isolation

Abstract

The method for making shallow trench isolation at least includes the following steps: firstly, successively forming pad oxide layer and silicon nitride layer on the substrate, patterning silicon nitride layer and pad oxide layer to expose partial substrate surface, etching the exposed substrate surface to form trench in the substrate, then thermally-oxidating surface of trench to form lined oxide layer on the surface of the trench, then further forming conformal silicon-enriched oxide layer on the surface of substrate and trench, and forming silicon oxide layer on the silicon-enriched oxide layer, filling up said trench, using chemical mechanical grinding method to remove silicon oxide layer high than silicon nitride layer, then successively removing silicon nitride layer and pad oxide layer so as to form shallow trench isolation.

Description

technical field [0001] The present invention relates to a manufacturing method of an integrated circuit, and in particular to a manufacturing method of shallow trench isolation (Shallow Trench Isolation). Background technique [0002] The element isolation region is used to prevent carriers (Carrier) from moving between adjacent elements through the substrate, such as forming an element isolation region between adjacent metal oxide field effect transistors (MOSFET, hereinafter referred to as MOS transistors), To reduce the charge leakage (Charge Leakage) generated by the MOS transistor. In the process of VLSI or ULSI, since the number of transistors is very large and dense, in order to prevent a short circuit (Short Circuit) between adjacent transistors, an isolation structure must be formed between these adjacent transistors. With the improvement of component integration and the reduction of line width, shallow trench isolation has become a necessary component isolation st...

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Problems solved by technology

[0003] However, in the process of removing the pad oxide layer formed by thermal oxidation, because the etching rate of silicon oxide deposited by chemical vapor deposition is greater than that of the pad oxide layer formed by thermal oxidation, it often causes The edge of the silicon oxide plug is dimpled

After the conductive material of the gate is subsequently deposited and the gate is defined, some conductive material is often left in the edge recess of the silicon oxide plug, which affects the electrical characteristics of the semiconductor device, such as the sub-threshold current. increase, etc., causing serious operational problems for various semiconductor components

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