Multi-chip stacking structure

Abstract

The invention discloses a multi-chip stacking structure, which comprises a bottom layer, a first chip, at least two stack chips and a non-conductor layer, wherein the bottom layer is a substrate provided with a circuit reconfiguration layer; the first chip at least comprises a non-conductor layer and a metal layer; the non-conductor layer is provided with a metal filling channel; the metal layer is invertedly arranged on the circuit reconfiguration layer of the bottom layer; the at least two stack chips are stacked upwards in turn; each stack chip at least comprises a metal layer; the non-conductor layer is provided with a metal filling channel; the metal filling channel is electrically connected with the metal layers of the correspondingly stacked stack chips; and the metal filling channel of the non-conductor layer stacked downmost is electrically connected with the metal filling channel of the non-conductor layer of the first chip. Due to the structure, the increase of complexity of a heat dissipation design due to the increase of the number of metal filling layers can be greatly improved, and the heat dissipation efficiency is improved.

Description

technical field [0001] The present invention relates to a multi-chip stacking structure, in particular to a multi-chip stacking structure with a good electrical planning structure and a multi-chip stacking structure through metal filling channels. Background technique [0002] In order to improve the performance and capacity of semiconductor packages, in order to comply with the trend of small or portable electronic products that are increasingly focused on thinner, smaller and higher performance, the demand for semiconductor devices that can increase the density of chips is also increasing. [0003] The traditional two-dimensional integrated single system chip (system-on-chip, SOC), with the help of the industry commonly known as Moore's Law, through the semiconductor manufacturing process, the transistors on the chip are made smaller and smaller, so as to make smaller electronic products It can have better performance, but physicists found that when the gate used to contro...

AI Technical Summary

Problems solved by technology

[0008] (1) Lack of EDA design tool assistance;

[0009] (2) Increasing TSV settings may increase the complexity of thermal design;

[0011] (4) Combination of different functional systems; and

[0012] (5) Specifications and standards are not uniform

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