PLD architecture optimized for 10G Ethernet physical layer solution

Abstract

An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

Description

technical field [0001] The present invention relates to integrated circuit devices, and more particularly to 10 Gigabit Ethernet (10GbE) physical (PHY) layer circuits for programmable integrated circuit devices. Background technique [0002] As the demand for network bandwidth increases, the adoption of 10GbE is gaining momentum for Local Area Networks (LANs), Wide Area Networks (WANs) and Metropolitan Area Networks (MANs). 10GbE is a version of Ethernet that has a nominal data rate of 10 gigabits per second and is specified by the IEEE 802.3ae standard. The IEEE 802.3ae standard is hereby incorporated by reference in its entirety. Due to the high speed and demanding specifications of the 10GbE standard, especially at the physical layer (PHY layer), performance is a key differentiator among network equipment vendors. [0003] The PHY layer of 10GbE can be achieved by integrating a large number of available components, which communicate through standard interfaces. For exa...

AI Technical Summary

Problems solved by technology

However, these implementations do little to reduce the complexity of 10GbE tools

Extensive bus protocols required to connect optical modules to PLDs are quite complex and cause performance degradation

Typically, implementing these protocols within the PLD requires additional buffers, clock dividers, and reference clock signals, which add latency, timing constraints, and power consumption to the system

In addition, the optical modules that must be used in this implementation are expensive and have high power and space requirements compared to common optical transceivers

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