Interface logic for a multi-core system-on-a-chip (SOC)

Abstract

In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Description

technical field [0001] The present invention relates to interface logic for a multi-core system-on-chip (SOC). Background technique [0002] As semiconductor technology evolves, a greater number of functional properties are combined on a single semiconductor die. While separate integrated circuits may have previously existed to provide different functions such as processing functions, control functions, interface functions, etc., modern semiconductors are able to combine multiple functions such as these functions in a single integrated circuit. [0003] Evidence of this trend is the continuously increasing number of available system-on-chip (SoC) devices. These single-die integrated circuits (ICs) include various circuits such as processing circuits, interface circuits, application specific function circuits, and the like. Therefore, portable devices such as mobile terminals, netbooks, and the like and embedded devices can be realized with a smaller number of devices. Thi...

AI Technical Summary

Problems solved by technology

Typically, SoCs include single-core processors, which can place limits on their usefulness

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