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Chip structure for preventing latch-up effect and method thereof

A latch-up effect and chip structure technology, applied in the direction of transistors, electrical components, electrical solid-state devices, etc., can solve the problems of increasing the distance between the driver and other modules, increasing the layout area, etc.

Inactive Publication Date: 2011-07-20
SUZHOU HUAXIN MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to overcome this problem, people generally use methods such as adding a majority carrier multi-carrier guard ring (the guard ring is grounded) in the driver module and other modules, increasing the distance between the driver and other modules, and increasing the distance between the driver and other modules. etc. (see figure 2 ), but this method will increase the layout area

Method used

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  • Chip structure for preventing latch-up effect and method thereof
  • Chip structure for preventing latch-up effect and method thereof
  • Chip structure for preventing latch-up effect and method thereof

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Embodiment Construction

[0012] Aiming at the deficiencies of the existing technical solutions for preventing the latch-up effect in the chip, the present invention proposes to add an nwell minority carrier protection ring between the drive module and the majority carrier protection ring of other modules including the digital-analog module programs such as image 3 shown.

[0013] Because the minority carrier guard ring is to collect electrons in advance, and the minority carrier guard ring is deep, the effect is quite obvious, and it can reduce the current gain of the parasitic lateral transistor Q1, that is, βnpn.

[0014] Correspondingly, the majority carriers collect holes. But because it is a P-type substrate, holes must enter the substrate, and the majority carrier guard ring essentially reduces the local resistance. After the minority carrier protection ring is added, the p+ type majority carrier protection ring is closer to the nwell, which is more conducive to early collection, and the effe...

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Abstract

The invention relates to a chip structure for preventing latch-up effect and a method thereof. The method comprises the following steps: adding nwell minority carrier guard rings between a driving module of a chip and other modules, enabling the concentration of a substrate which is near to the minority carrier rings to reduce, increasing the resistance of the substrate, and further preventing the generation of the latch-up effect in the chip. Further, the nwell minority carrier rings are connected with 0 potential. The chip structure mainly comprises the driving module and other modules with a digital-analog module, and the nwell minority carrier guard rings are loaded between the driving module and other modules. By adopting the chip structure and the method, the good effect of preventing the latch-up effect can be generated under the premise of not increasing the area of a layout, and the normal working performance of the chip can not be affected.

Description

technical field [0001] The invention relates to a chip structure and method capable of preventing latch up (latch-up effect) in the technical field of integrated circuits. Background technique [0002] With the development of IC manufacturing technology, the chip packaging density and integration level are getting higher and higher, and the possibility of latch up will become larger and larger. Generally speaking, the conditions for latch up are: the loop current gain is greater than 1, βnpn βpnp>=1; both BJT emitters are in forward bias; a current larger than the PNPN device maintenance current can be formed at the emitter. Due to the large current on the output stage of the drive circuit, a certain displacement current will be generated in the substrate close to the drive device. When this current flows through the low-voltage part, there will be a potential drop on the parasitic resistance Rp. Refer to figure 1 , when the potential reaches a certain value, this part o...

Claims

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Application Information

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IPC IPC(8): H01L27/092H01L27/02H01L21/82
Inventor 彭秋平杭晓伟张祯江石根杜坦
Owner SUZHOU HUAXIN MICROELECTRONICS
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