TSV (through silicon via) chip bonding structure

A chip bonding and bonding structure technology, applied in the field of microelectronics, can solve problems such as non-solutions, and achieve the effect of preventing lateral offset and precisely aligning contacts
CN102157459AInactive Publication Date: 2011-08-17PEKING UNIV
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
PEKING UNIV
Publication Date
2011-08-17
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

The invention discloses a TSV (through silicon via) chip bonding structure, belonging to the technical field of micro electronics. The bonding structure comprises a first chip and a second chip, wherein the first chip comprises a first micro bump and first surrounding structures around the first micro bump; the height of the first surrounding structures is more than that of the first micro bump; the second chip comprises a second micro bump; the second micro bump is embedded into the first surrounding structures and the first surrounding structures restrict lateral displacement of the second micro bump; the second chip also comprises second surrounding structures; and the first surrounding structures are embedded into the second surrounding structures and the second surrounding structures restrict lateral displacement of the first surrounding structures. The TSV chip bonding structure can be used in such fields as manufacturing of semiconductor devices and the like.
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Description

technical field

[0001] The invention relates to a TSV (Through Silicon Via, through-silicon via) chip three-dimensional integration technology, in particular to a design of a TSV bonding layer structure, and belongs to the field of microelectronic technology. Background technique

[0002] Today's semiconductor industry generally believes that TSV-based chip three-dimensional integration technology is one of the important technologies that can make chips continue to develop along the blueprint of Moore's Law. For the stacking of TSV chips, one of the common and reliable methods at present is to perform intermetallic bonding between micro bumps (micro bumps) through solder to form an intermetallic compound (IMC). IMC has a higher melting point and can be bonded to another layer of chips.

[0003] Such as figure 1 As shown, 101 and 102 are TSV chips, 103 and 104 are conductive vias, and 105 and 106 are conductive micro-bumps. Generally, 105 and 106 are bonded by solder 107 ....

Claims

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