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Operating method of memory element

A technology of memory elements and storage areas, applied in static memory, read-only memory, information storage, etc., can solve the problems of misjudgment of memory state, starting voltage difference, complicated detection, etc. Effect

Active Publication Date: 2014-09-24
ACER INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, these multi-bit memory methods need to have a sufficiently large initial voltage difference to avoid misjudgment of the memory state
In addition, the number of electrons injected into the floating gate must be quite accurate, so the detection is more complicated, and it causes problems of durability and durability

Method used

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Embodiment Construction

[0033] The present invention discloses an operation method of a memory element, which stores three-bit data on the same memory cell by storing charges in the charge storage layer near the source, drain and channel of the memory, and To achieve three-bit memory effect. The following will match Figures 1 to 5D The drawings describe some preferred embodiments of the present invention, wherein the same reference numerals represent the same or elements with the same function, and the accompanying related drawings are not drawn according to actual scale, and their role is only to express the structural features of the present invention . In addition, the devices, components and method steps described in the following embodiments are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. It should be noted that when the following description refers to an element on top of another element, it may mean that the element is dir...

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Abstract

The present invention provides an operating method of a memory element. This method stores charges in the source storage area, the drain storage area, and the channel storage area of ​​the charge storage layer located above the source, drain, and channel of the SONOS transistor. A single storage cell has a three-dimensional memory effect. The charges in the channel storage area are written and erased using the FN tunneling method; the charges in the source storage area and the drain storage area are written using the channel hot electron injection method, and the charges are transferred using the unilateral FN tunneling method. Erase. The present invention can store three-digit data in a single storage cell, greatly increasing the memory density of the memory.

Description

technical field [0001] The invention relates to an operation method of a memory element, more specifically, the invention relates to an operation method of a memory element which enables a single transistor to have a multi-bit memory effect. Background technique [0002] The two-bit memory effect of general SONOS (silicon-oxide-nitride-oxide-silicon) memory is to use channel hot electrons and other writing methods to store electrons in the silicon nitride layer near the source or drain terminal, so that a single memory The source and drain of the cell can store information independently, achieving a two-bit effect. [0003] To achieve a memory effect of more than two bits, a multi-level cell (MLC) technology can be used to store different numbers of electrons on the floating gate, so that the memory has multiple start-up voltages. Then, the corresponding current is read by applying a read voltage between different starting voltages, so as to distinguish different memory sta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06
Inventor 张鼎张简富彦陈世青陈德智
Owner ACER INC
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