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P-type MOS (Metal Oxide Semiconductor) memory cell

A storage unit and memory technology, applied in electrical components, transistors, electric solid state devices, etc., can solve the problems of increasing the size of the storage unit and affecting the performance of the storage unit.

Inactive Publication Date: 2011-09-07
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, the size of the storage unit is inevitably increased, and the above-mentioned interference will also affect the performance of the storage unit.

Method used

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  • P-type MOS (Metal Oxide Semiconductor) memory cell
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  • P-type MOS (Metal Oxide Semiconductor) memory cell

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Embodiment Construction

[0030] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0031] Figure 6 A schematic diagram showing the structure of a P-type memory cell according to an embodiment of the present invention.

[0032] Figure 6 The illustrated P-type MOS memory cell includes a source active region S, a gate active region, and a drain active region D arranged on a substrate P-Sub. The select gate SG, the control gate CG, and the floating gate FG are arranged above the gate active region, wherein the floating gate FG is arranged below the control gate CG. Wherein in the horizontal direction from the source active region S to the drain active region D, the select gate SG and the floating gate FG are sequentially arranged, and the control gate CG is in a floating position in the vertical direction (perpendicular to the...

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Abstract

The invention relates to a P-type MOS (Metal Oxide Semiconductor) memory cell comprising a source electrode active region, a grid electrode active region and a drain electrode active region, a selection grid electrode, a control grid electrode and a floating grid electrode, wherein the source electrode active region, the grid electrode active region and the drain electrode active region are arranged on a substrate; the selection grid electrode, the control grid electrode and the floating grid electrode are arranged above the grid electrode active region; the floating grid electrode is arranged below the control grid electrode; and the selection grid electrode is closer to the source electrode active region in comparison with the control grid electrode and the floating grid electrode and the control grid electrode and the floating grid electrode are closer to the drain electrode active region in comparison with the selection grid electrode. According to the invention, the interference is eliminated and the size is reduced by regulating a structure of the P-type MOS memory cell.

Description

technical field [0001] The invention relates to the field of memory design, in particular to a P-type MOS storage unit used in a flash memory. Background technique [0002] In the design of memory (especially flash memory), the design of the storage unit that makes up the memory is a very important link; the reason is that the performance of the storage unit determines the overall performance of the memory, and the size of the storage unit also determines the overall size of the memory. . [0003] The prior art proposes a figure 1 The structure of the P-type memory cell is shown, and the structure of the P-type memory cell has the advantage of smaller size. Wherein, the memory cell includes a source active region S, a middle active region D*, and a drain active region D arranged in an N well in the substrate P-Sub; and the source active region S and the middle have The floating gate FG and the control gate CG are arranged in the upper part of the region between the source...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/788H01L27/115H10B69/00
Inventor 董耀旗李荣林孔蔚然宗登刚徐爱斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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