Multi-channel bridge and bus system

Abstract

The invention relates to the chip design field, and discloses a multi-channel bridge and a bus system. The multi-channel bridge comprises a decoding arbitration unit and a plurality of conversion units, and each conversion unit is connected with the decoding arbitration unit separately. The plurality of conversion units provide a plurality of independent access channels, and by using the decodingarbitration unit to control the access channels, a master device can access a high-speed slave device via the independent channels, and the master device is not be obstructed due to the slow responsespeeds of some devices in the system bus, improving the overall efficiency of the system.

Description

technical field [0001] The present invention relates to the field of chip design, in particular to the design of a System on Chip ("SoC" for short). Background technique [0002] A SoC is an integrated circuit with a specific purpose, which contains the complete system and has all the content of the embedded software. At the same time, it is also a technology to realize the whole process from determining the system function, to software / hardware division, and to complete the design. From a narrow point of view, it is the chip integration at the core of an information system, which integrates key components of the system on a chip; from a broad point of view, SoC is a micro-miniature system. [0003] Today's SoC usually includes one or more MASTER (master device) and a set of system bus, MASTER is connected to the bus through the MASTER interface conversion circuit, so as to achieve the purpose of accessing each slave device on the bus; and each slave device is also through ...

AI Technical Summary

Problems solved by technology

[0006] The disadvantage of MASTER accessing SDRAM / DDR through the system bus is that it needs to share the system bus with the DMA controller during access. Since programs and data are usually loaded into SDRAM from off-chip non-volatile memory, such as NANDFLASH and hard disk, MASTER needs to access SDRAM frequently, and the DMA controller also has to compete for the bus, which reduces the efficiency of program execution, which in turn reduces the real-time performance of DMA transmission (some applications such as playing audio and video, recording, video, etc., There are certain code rate and sampling rate requirements)

[0007] Another reason for this shortcoming is that most of the popular bus protocols in the past, such as the AMBA bus protocol, do not support multiple commands. If the previous command is not processed, the subsequent commands will be blocked; therefore, even if there is no DMA controller Competing for the bus, only when the MASTER accesses the bus device, if the response speed of the previous device is relatively slow, the following instruction fetching or reading and writing data will be blocked, reducing the execution efficiency of the entire system

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