Time sequence adjustment module and method, and a two-wire transmission system

Abstract

The invention discloses a time sequence adjustment module for adjusting time sequences and clocks of a plurality of chips respectively. The time sequence adjustment module comprises a time sequence storage unit for storing the time sequences and the clocks which correspond to the plurality of chips respectively, and a time sequence adjustment unit which is coupled to the time sequence storage unit and used for adjusting the time sequences and the clocks which correspond to the plurality of chips, storing the time sequences and the clocks into the time sequence storage unit, receiving a pointer signal of one of the plurality of chips and outputting information of the time sequence and the clock of the chip.

Description

technical field [0001] The invention refers to a timing adjustment module, a second-line transmission system and a timing adjustment method, especially a timing adjustment module, a second-line transmission system and a timing adjustment method capable of adjusting the timing and clocks of multiple chips. Background technique [0002] The bus is a communication tool between the master device (master) and the slave device (slave), used for data, clock, address transmission, divided into two types: serial and parallel. Among them, the serial bus transmits multiple data sequentially on the same data line (one bit at a time point), instead of transmitting several bits at a time by several lines like parallel, so it saves more pins than the parallel bus . In the serial bus system, the master device (or slave device) uses an interface circuit to output a single-ended logic signal, and the slave device (or master device) judges the received data according to the logic level. Amon...

AI Technical Summary

Problems solved by technology

[0007] However, this method may be mutually exclusive due to the timing of different chips. For example, the maximum hold time of the chip in the slave device SLA_1 is 300 nanoseconds, while the minimum hold time of the chip in the slave device SLA_2 is 400 nanoseconds, making it impossible to find a common timing.

In addition, because the timing control of the software controller for input / output pin emulation is achieved by software, once an interrupt (Interrupt) is encountered or under an operating system with a priority preemptive (Priority Preemptive) function, it may be blocked by other Jobs with higher priority take control

In this way, it is possible to increase the time for the more sensitive hold time

In addition, in order to save power consumption, some microprocessors (microprocessors) will reduce their clocks when they communicate with the host through two-wire transmission, and cannot accept the standard 100 kHz clock of the internal integrated circuit bus.

[0008] Therefore, when the known technology faces different chip combinations, it is necessary to adjust different general timings, which is very time-consuming, and it may not be possible to find a universal timing at all; for devices that do not need to use 100 kHz, it cannot be reduced. its clock, causing unnecessary power consumption

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