Fully balanced dual-port memory cell

Abstract

The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU1 and PU2) configured with the four pull-down devices to form two cross-coupled inverters, wherein two of the pass-gate devices are configured to form a first port and another two of the pass-gate devices are configured to form a second port.

Description

technical field [0001] The invention relates to a memory, in particular to a static random access memory unit. Background technique [0002] In deep sub-micron integrated circuit technology, embedded static random access memory devices have become the main storage unit in high-speed communication, image processing and single-chip system products. For example, dual-channel SRAM devices can allow parallel operations, such as simultaneous reading and writing or two simultaneous read operations in one cycle, so dual-channel SRAM devices are more efficient. Single-channel SRAM devices have higher bandwidth. In the advanced technology of embedded memory and system-on-a-chip products, the low loading and high-speed characteristics of the static random access memory cell structure are its important characteristics. Thin SRAM cell structure with short bit lines has better performance in terms of RC delay of the bit lines. [0003] However, the thin SRAM cell structure still encoun...

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Problems solved by technology

[0005] It can be seen that the above-mentioned existing embedded static random access memory device obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.

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