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Solid-state imaging device

A technology of solid-state imaging device and pixel array, which is applied in the directions of image communication, TV, color TV components, etc., can solve the problems of time-consuming data transmission, increasing the number of columns, and increasing the scale of data transmission circuits.

Inactive Publication Date: 2013-09-11
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in recent years, the number of pixels equipped with CMOS image sensors tends to increase, and with the increase in the number of pixels, the number of columns also increases.
Therefore, the conventional transmission method in which data is transmitted by one bit per column increases the circuit size of the data transmission circuit, causing a problem that data transmission takes time.

Method used

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Examples

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no. 1 example ）

[0051] figure 2 It is a block diagram showing the configuration of main parts of the solid-state imaging device of the first embodiment. In this first embodiment, a configuration example is shown in which 2 bits are transferred every 2 columns when the number of transfer bits n of each data transfer circuit is n=2. figure 2 In addition to the sampling and holding signal conversion circuit group 4a, the column selection circuit 5a, the image data receiving circuit 6a, the signal processing circuit 7, and the reference voltage driving circuit group 8a, a control signal driving circuit group 15 is also shown.

[0052] figure 2 Among them, the column selection circuit 5a repeatedly outputs the column selection signal in the relationship of sequentially specifying each of the two columns of the pixel array 2 sequentially at predetermined time intervals. Each column selection signal is input to the sample-and-hold signal conversion circuit group 4 a , the reference voltage driv...

no. 2 example ）

[0083] Figure 10 It is a block diagram showing the configuration of main parts of the solid-state imaging device of the second embodiment. In this second embodiment, a configuration example is shown in which 2 bits of the same column are transferred when the number of transfer bits n of each data transfer circuit is n=2.

[0084] Figure 10 is in figure 2 In the configuration shown in the first embodiment, a sample-hold signal conversion circuit group 4b is provided instead of the sample-hold signal conversion circuit group 4a, and a column selection circuit 5b is provided instead of the column selection circuit 5a. The other configurations are the same, and the same symbols are given. Among them, the description will focus on the part related to the second embodiment.

[0085] In this second embodiment, the column selection circuit 5 b repeatedly outputs a column selection signal in a relationship of sequentially specifying each column of the pixel array 2 at predetermi...

no. 3 example ）

[0094] Figure 12 It is a block diagram showing the configuration of main parts of the solid-state imaging device of the third embodiment. In this third embodiment, a configuration example in the case of performing 1-bit transmission is shown as in the general configuration. Such as Figure 12 shown in Figure 10 In the configuration shown in (Second Embodiment), the signs of elements other than the column selection circuit 5 b , the control signal drive circuit group 15 , and the signal processing circuit 7 are changed.

[0095] Figure 12 In the sample-and-hold signal conversion circuit group 4c, a data transfer circuit 18c for performing 1-bit transfer is provided for each 1-bit register circuit 1 in each column direction. Therefore, the number of data lines 10 is ten. The N data transmission circuits 18c arranged in the row direction are respectively configured as, for example, Figure 13 As shown, one data line 10 is driven in parallel according to the column select...

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Abstract

According to one embodiment, the data transfer circuit outputs n bits for each N columns (n>=2) in the pixel array among digital data of a predetermined number of bits digitally converted in accordance with the column selection signal which collectively and sequentially selects N columns (N>=2) in the pixel array by using one data line. One data line is commonly and correspondingly connected to one differential input terminals of 2n-1 differential amplifier circuits arranged in the column direction in an input stage of the signal processing circuit, and corresponding one of 2n-1 reference voltage lines is connected to the other differential input terminals.

Description

[0001] This application enjoys the benefit of the priority of Japanese Patent Application No. 2010-068765 filed on March 24, 2010, the entire contents of which are incorporated herein by reference. technical field [0002] This embodiment relates to a general solid-state imaging device. Background technique [0003] As a solid-state imaging device, for example, a CMOS image sensor is configured such that a sample-hold signal conversion circuit disposed in each column of a pixel array reads a voltage signal output by each pixel in a selected row of the pixel array according to the amount of light and converts it into a digital signal. , the sample-and-hold signal conversion circuit after column selection sequentially transmits the converted digital signal to the signal processing circuit for image processing, so as to obtain a prescribed two-dimensional image. [0004] The sample-and-hold signal conversion circuit has an analog-to-digital converter (ADC) that converts the vol...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N5/374H04N5/378H04N25/00
CPCH04N5/378H04N5/374H04N25/76H04N25/78H04N25/75
Inventor 中村健一
Owner KK TOSHIBA
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