Instruction optimization method and processor for AES (Advanced Encryption Standard) symmetric encryption algorithm

A symmetric encryption algorithm and instruction optimization technology, applied in the direction of machine execution devices, etc., can solve the problems of not considering the AES algorithm instruction set expansion, the improvement effect of the AES algorithm execution efficiency is not very obvious, etc., to save memory space and code memory. space, and the effect of improving execution efficiency

Inactive Publication Date: 2011-10-19
SHANDONG UNIV
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Problems solved by technology

However, the work carried out by the above two inventions only performs instruction optimization and expansion operations for a certain computing module o

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  • Instruction optimization method and processor for AES (Advanced Encryption Standard) symmetric encryption algorithm
  • Instruction optimization method and processor for AES (Advanced Encryption Standard) symmetric encryption algorithm
  • Instruction optimization method and processor for AES (Advanced Encryption Standard) symmetric encryption algorithm

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Embodiment Construction

[0031] Below in conjunction with accompanying drawing and embodiment the present invention will be further described:

[0032] An AES symmetric encryption algorithm extended instruction set optimization method, under the premise of not changing the length of the original processor instruction opcode, the number of instruction bits and not affecting the operating speed of the processor, the optimization operation is:

[0033] 1) For the bit-fetching operation in the S-box byte replacement process, each bit of the eight-bit binary number needs to be taken out for each affine transformation. However, in the ARM processor and other commonly used embedded processors, there is no direct bit-fetching operation. The traditional method needs three assembly instructions to complete the bit-fetching operation, and needs to be executed for three clock cycles, so the execution process is very time-consuming. In order to speed up the process, the instruction getbit was designed and ad...

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Abstract

The invention discloses an instruction optimization method and an instruction processor for AES (Advanced Encryption Standard) symmetric encryption algorithm, wherein the instruction processor mainly comprises four parts of: a data memory, a code memory, a register file and an assembly line, wherein the assembly line comprises an addressing unit, a decoding unit, an execution unit and an assembly line controller. With the instruction optimization method, in the aspect of execution efficiency is reduced by 57.3x% relative to an ARM (Advanced RISC Machines) processor in a way that the clock periodicity required for AES_ASIP performing AES encryption algorithm is counted through periodic emulation, so that the execution efficiency of the algorithm is greatly improved; and in the aspect of code space, the instruction code occupies 783 bytes of memory space on the ARM processor, while the instruction code on the AES_ASIP just occupies 416 bytes of memory space, so that 46.6x% of code memory space is saved.

Description

technical field [0001] The invention relates to the field of encryption and decryption of the AES symmetric encryption algorithm, in particular to an AES special instruction set processor and an instruction optimization method thereof. Background technique [0002] The AES algorithm brings together the advantages of strong security, high performance, high efficiency, ease of use and flexibility for data encryption. However, since the encryption and decryption process takes up more processor resources, the performance of the processor becomes the main limiting factor for the efficient operation of the encryption algorithm. Although the performance of microprocessors is constantly improving, the execution efficiency of encryption algorithms in many fields cannot meet all computing design requirements, especially in embedded environments with limited computing resources. Due to the low performance and slow operation speed of embedded microprocessors, the efficiency of encrypti...

Claims

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Application Information

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IPC IPC(8): G06F9/30
Inventor 夏辉贾智平陈仁海张志勇颜冲
Owner SHANDONG UNIV
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