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Method for generating system model and method transmitting data in same

A technology for transmitting data and models, applied in the field of transmitting data

Active Publication Date: 2014-04-02
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The challenge of functionally verifying such complex devices is exponentially challenging when utilizing the millions of transistors that can be used to build large and complex single chips at 65 nanometer (nm) and smaller process fabrication technologies. growing up

Method used

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  • Method for generating system model and method transmitting data in same
  • Method for generating system model and method transmitting data in same
  • Method for generating system model and method transmitting data in same

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Embodiment Construction

[0061] Software development in RTL is challenging due to the slow simulation speed of RTL design. Simulation speeds in the millions of cycles per second range are instructive for software development, while RTL typically provides simulation speeds of less than 100 to 200 cycles per second. The use of hardware accelerators and emulators has increased rapidly, reaching the cycles per second throughput that leads to software development. However, hardware accelerators or emulators can only be used if an RTL or gate-level design is available. Before the RTL design information is ready, it is too late in the design cycle to make architectural changes to develop software that performs optimally and has precise functionality. A lot of project plans are cancelled or too late due to delays in software development. Therefore, there is a need for a platform or tool to develop software prior to design at the RTL or gate level, and this platform or tool is provided in various embodiments...

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Abstract

A method of transmitting data is disclosed. At least one system block of a system-on-chip (SoC) is modeled at an untimed functional level in first and second untimed functional models. First and second transaction level (TL) models of the at least one system block system block are modeled at a transaction level (TL) using the first and second untimed functional models, respectively. First and second cycle accurate (CA) models are modeled at a cycle accurate (CA) level using the first and second TL models, respectively. Data is transmitted from the first untimed functional model to the first CA model, from the first CA model to the second CA model via a CA bus, and from the second CA model to the second untimed functional model.

Description

technical field [0001] The present invention relates to a method of generating a system model and a method of transmitting data in the system model. Background technique [0002] Integrated circuit (IC) technology continues to increase in complexity due to improvements in semiconductor manufacturing techniques. Complete System-on-Chip (SoC) solutions involving many components such as processors, timers, interrupt controllers, buses, memory and / or embedded software on a single circuit are now available in a wide variety of in the application. Software development, early hardware architecture exploration, and functional verification of complex SoC or processor devices are challenges faced by the semiconductor industry. The challenge of functionally verifying such complex devices is exponentially challenging when utilizing the millions of transistors that can be used to build large and complex single chips at 65 nanometer (nm) and smaller process fabrication technologies. gr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F2217/86G06F17/5022G06F2117/08G06F30/33G06F30/367
Inventor 阿肖克·梅塔
Owner TAIWAN SEMICON MFG CO LTD
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