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Termination circuit for on-die termination

An on-chip termination and circuit technology, applied to circuits, electrical components, and generating electric pulses, can solve problems such as power consumption and inflexibility

Inactive Publication Date: 2012-03-28
CONVERSANT INTPROP MANAGEMENT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, traditional on-chip termination techniques are often relatively power hungry and / or inflexible

Method used

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  • Termination circuit for on-die termination
  • Termination circuit for on-die termination
  • Termination circuit for on-die termination

Examples

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Embodiment Construction

[0024] now refer to figure 1 with figure 2 , shows a termination circuit 500 for the on-chip termination of terminals 14 connected to the inner region 16 of the semiconductor device 100 , 200 . On-chip termination may be used to protect the integrity of signals transmitted and / or received via terminal 14 . Accordingly, the terminal 14 may be an input terminal, an output terminal or a bidirectional input / output terminal. In certain non-limiting embodiments, terminals 14 may be configured to transmit and / or receive data signals that vary between two voltage levels representing corresponding logic values. The semiconductor device 100, 200 including the internal region 16 and the terminal 14 may be a memory chip (such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, etc.) or can benefit from chip Any other type of semiconductor device terminated within.

[0025] Although the termination circuit 500 is shown as being connected wi...

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Abstract

In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 61 / 151886 filed February 12, 2009 in the name of Peter B. Gillingham, the inventor of which is incorporated by reference under 35 USC § 119(e) of the United States Patent Act here. Background technique [0003] When a signal travels along a path with an impedance discontinuity (or "mismatch"), the signal is partially reflected. The reflected signal interferes with the original signal and this can lead to loss of signal integrity and incorrect signal levels detected by the receiver. To mitigate the occurrence of signal reflections, it is beneficial to place circuits with equivalent impedance at the point of the discontinuity. This is called "finishing". For example, resistors can be placed on a computer motherboard to terminate a high-speed bus. [0004] Although terminating resistors reduce reflections at the ends of a signal path,...

Claims

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Application Information

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IPC IPC(8): H03H11/46G11C5/06H01L23/50
CPCH03K3/012H03K19/00361H03K19/0005H04L25/0278H01L2924/0002H01L2924/00G11C5/14G11C7/10G11C7/1051G11C7/22G11C11/4076
Inventor P·B·吉灵厄姆
Owner CONVERSANT INTPROP MANAGEMENT INC
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