Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same

Abstract

The invention discloses a Sigma-Delta modulator and a Sigma-Delta analog to digital converter containing the modulator. The modular comprises a first gain unit, a first analog subtractor, a first delay integrator, a third gain unit, a second analog subtractor, an integrating circuit structure, a fifth gain unit and a quantizer which are sequentially connected from an input end to an output end, a first feedback DAC (Digital-to-Analog Converter), a first analog differentiator and a second gain unit which are sequentially connected from an output end of the quantizer to the first analog subtractor, and a second feedback DAC, a second analog differentiator and a fourth gain unit which are sequentially connected from the output end of the quantizer to the second analog subtractor; a signal output by the first gain unit and a signal output by a first feedback passageway are differed by the first analog subtractor; and a signal output by the third gain unit and a signal output by a second feedback passageway are differed by the second subtractor. According to the invention, the digital logical delay of DAC feedback passageways can be eliminated when assemblies of reforming feedback DACmismatch.

Description

technical field [0001] The invention relates to the technical field of an analog-to-digital converter and integrated circuits for signal processing, in particular to a Sigma-Delta modulator and a Sigma-Delta analog-to-digital converter comprising it. Background technique [0002] Due to the application of oversampling and noise shaping techniques, Sigma-Delta data conversion technology has been widely used in wired and wireless communication systems with low to medium frequency bandwidth, high precision, low voltage and low power consumption. Among various Sigma-Delta modulator (SDM) structures, multi-bit topology has obvious advantages over single-bit topology because of its lower quantization noise level and higher stability. However, the non-linearity problem caused by the mismatch of the internal components of the feedback digital-to-analog converter (DAC) in the multi-bit structure severely restricts its performance. [0003] In order to overcome the above-mentioned no...

AI Technical Summary

Problems solved by technology

Although this additional digital integrator is smaller than the feedback digital logic delay introduced by the general DWA algorithm, as the number of bits of the feedback DAC increases, this delay will become larger and larger, thereby increasing the delay time of the entire loop and causing timing delays. tension or even errors, thereby degrading the performance of the SDM

Also, the mismatch between the additional unit feedback DAC branch introduced to implement this digital integrator and the original multi-bit feedback DAC branch will limit the input signal level of the overall SDM

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