Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same

A modulator and quantizer technology, applied in the field of Sigma-Delta analog-to-digital converters, can solve problems such as timing tightness, increase the entire loop delay time, errors, etc., achieve shaping improvement, eliminate transfer function changes, and eliminate digital logic. delayed effect

Active Publication Date: 2012-04-18
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this additional digital integrator is smaller than the feedback digital logic delay introduced by the general DWA algorithm, as the number of bits of the feedback DAC increases, this delay will become larger and larger, thereby increasing the delay time of the entire loop and causing ti

Method used

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  • Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same
  • Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same
  • Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0064] Example 1:

[0065] like figure 2 As shown, a Sigma-Delta modulator is described in this embodiment, including:

[0066] The first gain unit 210, the gain coefficient is b, and the input terminal is connected to the input signal U of the modulator;

[0067] The first analog subtractor 220 makes a difference between the signal output by the first gain unit 210 and the signal output by the first feedback path;

[0068] The first delay integrator 230, the input end is connected to the output end of the first analog subtractor 220;

[0069] The third gain unit 240, the gain coefficient is c 1 , the input terminal is connected to the output terminal of the first delay integrator 230;

[0070] The second analog subtractor 221 makes a difference between the signal output by the third gain unit 240 and the signal output by the second feedback path and the signal output by the internal feedback path;

[0071] The input end of the second delay integrator 231 is connected to...

Example Embodiment

[0117] Embodiment 2:

[0118] In the first embodiment, since the non-delay integrator 232 is introduced, it is equivalent to adding an active integrator, which will increase the line and power consumption. In order to overcome this problem, a double integrator structure is adopted in this embodiment. In addition, in order to reduce the output swing of the integrator, control it within a reasonable range, and increase the maximum input signal level, the gain coefficients of the Sigma-Delta modulator in this embodiment are adjusted accordingly. After a series of equivalent signal flow graph transformations in Embodiment 1, the structure of the modulator of this embodiment is obtained. The form is consistent with the first embodiment.

[0119] like image 3 As shown, this embodiment describes a Sigma-Delta modulator, including:

[0120] The first gain unit 310, the gain coefficient is s, and the input terminal is connected to the input signal U of the modulator;

[0121] The...

Example Embodiment

[0146] Embodiment three:

[0147] A sigma-delta analog-to-digital converter, the sigma-delta analog-to-digital converter comprises: the sigma-delta modulator described in the first embodiment or the second embodiment, which is used to filter the pre-anti-aliasing of an out-of-band input signal filter, and a digital filter for the backend to filter out high-frequency noise and reduce the sampling frequency.

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PUM

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Abstract

The invention discloses a Sigma-Delta modulator and a Sigma-Delta analog to digital converter containing the modulator. The modular comprises a first gain unit, a first analog subtractor, a first delay integrator, a third gain unit, a second analog subtractor, an integrating circuit structure, a fifth gain unit and a quantizer which are sequentially connected from an input end to an output end, a first feedback DAC (Digital-to-Analog Converter), a first analog differentiator and a second gain unit which are sequentially connected from an output end of the quantizer to the first analog subtractor, and a second feedback DAC, a second analog differentiator and a fourth gain unit which are sequentially connected from the output end of the quantizer to the second analog subtractor; a signal output by the first gain unit and a signal output by a first feedback passageway are differed by the first analog subtractor; and a signal output by the third gain unit and a signal output by a second feedback passageway are differed by the second subtractor. According to the invention, the digital logical delay of DAC feedback passageways can be eliminated when assemblies of reforming feedback DACmismatch.

Description

technical field [0001] The invention relates to the technical field of an analog-to-digital converter and integrated circuits for signal processing, in particular to a Sigma-Delta modulator and a Sigma-Delta analog-to-digital converter comprising it. Background technique [0002] Due to the application of oversampling and noise shaping techniques, Sigma-Delta data conversion technology has been widely used in wired and wireless communication systems with low to medium frequency bandwidth, high precision, low voltage and low power consumption. Among various Sigma-Delta modulator (SDM) structures, multi-bit topology has obvious advantages over single-bit topology because of its lower quantization noise level and higher stability. However, the non-linearity problem caused by the mismatch of the internal components of the feedback digital-to-analog converter (DAC) in the multi-bit structure severely restricts its performance. [0003] In order to overcome the above-mentioned no...

Claims

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Application Information

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IPC IPC(8): H03M3/02
Inventor 李宏义王源贾嵩张钢刚张兴
Owner PEKING UNIV
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