Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same

A modulator and digital technology, applied in the field of Sigma-Delta analog-to-digital converters, can solve the problems of increasing the delay time of the entire loop, tight timing, errors, etc., and achieve the elimination of digital logic delay, shaping improvement, and elimination of transfer function changes Effect

Active Publication Date: 2013-10-02
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this additional digital integrator is smaller than the feedback digital logic delay introduced by the general DWA algorithm, as the number of bits of the feedback DAC increases, this delay will become larger and larger, thereby increasing the delay time of the entire loop and causing timing delays. tension or even errors, thereby degrading the performance of the SDM
Also, the mismatch between the additional unit feedback DAC branch introduced to implement this digital integrator and the original multi-bit feedback DAC branch will limit the input signal level of the overall SDM

Method used

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  • Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same
  • Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same
  • Sigma-Delta modulator and Sigma-Delta analog to digital converter containing same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0065] Such as figure 2 As shown, a kind of Sigma-Delta modulator is described for this embodiment, including:

[0066] The first gain unit 210 has a gain factor of b, and its input terminal is connected to the input signal U of the modulator;

[0067] The first analog subtractor 220 is configured to make a difference between the signal output by the first gain unit 210 and the signal output by the first feedback path;

[0068] A first delay integrator 230, the input end of which is connected to the output end of the first analog subtractor 220;

[0069] The third gain unit 240, the gain coefficient is c 1 , the input terminal is connected to the output terminal of the first delay integrator 230;

[0070] The second analog subtractor 221 is configured to make a difference between the signal output by the third gain unit 240 and the signal output by the second feedback path, and then make a difference with the signal output by the internal feedback path;

[0071] A second ...

Embodiment 2

[0118] In the first embodiment, since the non-delay integrator 232 is introduced, it is equivalent to adding an active integrator, which will increase the circuit and power consumption. In order to overcome this problem, a double integrator structure is adopted in this embodiment. In addition, in order to reduce the output swing of the integrator, control it within a reasonable range, and increase the maximum input signal level, the gain coefficients of the Sigma-Delta modulator in this embodiment are adjusted accordingly. The structure of the modulator of this embodiment is obtained through a series of equivalent signal flow diagram transformations of Embodiment 1. Since this embodiment is obtained by performing equivalent signal flow diagram transformations on Embodiment 1, the transfer functions of the Form is consistent with embodiment one.

[0119] Such as image 3 As shown, this embodiment describes a Sigma-Delta modulator, including:

[0120] The first gain unit 310 ...

Embodiment 3

[0147] A Sigma-Delta analog-to-digital converter, the Sigma-Delta analog-to-digital converter comprising: the Sigma-Delta modulator described in embodiment one or embodiment two, used to filter the pre-anti-aliasing of the out-of-band input signal filter, and a digital filter used to filter out high-frequency noise and reduce the sampling frequency at the back end.

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Abstract

The invention discloses a Sigma-Delta modulator and a Sigma-Delta analog to digital converter containing the modulator. The modular comprises a first gain unit, a first analog subtractor, a first delay integrator, a third gain unit, a second analog subtractor, an integrating circuit structure, a fifth gain unit and a quantizer which are sequentially connected from an input end to an output end, a first feedback DAC (Digital-to-Analog Converter), a first analog differentiator and a second gain unit which are sequentially connected from an output end of the quantizer to the first analog subtractor, and a second feedback DAC, a second analog differentiator and a fourth gain unit which are sequentially connected from the output end of the quantizer to the second analog subtractor; a signal output by the first gain unit and a signal output by a first feedback passageway are differed by the first analog subtractor; and a signal output by the third gain unit and a signal output by a second feedback passageway are differed by the second subtractor. According to the invention, the digital logical delay of DAC feedback passageways can be eliminated when assemblies of reforming feedback DAC mismatch.

Description

technical field [0001] The invention relates to the technical field of an analog-to-digital converter and integrated circuits for signal processing, in particular to a Sigma-Delta modulator and a Sigma-Delta analog-to-digital converter comprising it. Background technique [0002] Due to the application of oversampling and noise shaping techniques, Sigma-Delta data conversion technology has been widely used in wired and wireless communication systems with low to medium frequency bandwidth, high precision, low voltage and low power consumption. Among various Sigma-Delta modulator (SDM) structures, multi-bit topology has obvious advantages over single-bit topology because of its lower quantization noise level and higher stability. However, the non-linearity problem caused by the mismatch of the internal components of the feedback digital-to-analog converter (DAC) in the multi-bit structure severely restricts its performance. [0003] In order to overcome the above-mentioned no...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M3/02
Inventor 李宏义王源贾嵩张钢刚张兴
Owner PEKING UNIV
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