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Memory device, host controller and memory system

A host controller and controller technology, applied in transmission systems, digital transmission systems, instruments, etc., can solve the problems of reduced transmission efficiency, reduced DMA effect, bit errors, etc., to achieve the effect of increasing data transmission efficiency

Inactive Publication Date: 2012-05-02
TOSHIBA MEMORY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This interrupts data transfer and reduces transfer efficiency
Especially when noise-induced interrupts like this occur during direct memory access (DMA) transfers using hardware, handling by the driver is necessary and the DMA is less effective
[0008] Transmission errors that occur due to noise or the like in data transmission using a high-speed bus cause the same problem; if a bit error occurs during data transmission due to noise when checking by CRC code etc., the host must interrupt data transmission once, and then retry the data transfer

Method used

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  • Memory device, host controller and memory system
  • Memory device, host controller and memory system
  • Memory device, host controller and memory system

Examples

Experimental program
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Embodiment Construction

[0019] Embodiments will be explained below with reference to the drawings.

[0020] figure 1 A storage system according to this embodiment is schematically shown.

[0021] In this embodiment, the argument of the command has a retransmission flag. This embodiment has a flow such that if an error occurs in response to an initial command, the host controller sets a retransmission flag and retransmits the same command as the initial command. Therefore, even when an error occurs during data transmission due to noise, it is possible to prevent interruption of data transmission and prevent reduction in data transmission efficiency.

[0022] figure 1 The illustrated system controller 11 is installed in a host device such as a cellular phone, and controls interfaces with a CPU 12, a system memory 13, and an SD host controller 14 of the host device.

[0023] System memory 13 stores host drivers 21 , descriptor tables 22 and data 23 . An operating system (OS) secures areas necessary...

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PUM

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Abstract

According to one embodiment, a host controller includes a command generator and detector. The command generator generates a command having a retransmission flag in an argument, and transmits the generated command to a memory device. The detector detects timeout if a response from the memory device cannot be recognized within a defined time. When transmitting an initial command, the host controller clears the retransmission flag and transmits the command. If the detector detects timeout, the host controller sets the retransmission flag, and retransmits the same command as the initial command to the device. If a normal response corresponding to the initial command or retransmitted command is received, the host controller recognizes that the command is correctly executed.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from Japanese Patent Application No. 2010-219780 filed on September 29, 2010; the entire contents of which are hereby incorporated by reference. technical field [0003] The embodiments described here generally relate to applications such as SD TM card and has an Advanced Direct Memory Access (ADMA) storage system. Background technique [0004] Recently, SD cards such as SD memory cards are widely used as host devices in, for example, cellular phones and digital cameras. Such an SD memory card is connected to a host device through a host controller, and the host controller controls data transfer between the host device and the SD memory card. [0005] As a host-device communication method using a bus interface, there is a method by which a host transmits a command to a device and checks whether the command is accepted by the device by receiving a response from the devi...

Claims

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Application Information

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IPC IPC(8): G06F13/28
CPCG06F11/1004H04L1/188H04L1/189H04L2001/125
Inventor 藤本曜久
Owner TOSHIBA MEMORY CORP
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