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Manufacturing method of wafer-level uniaxial strain silicon germanium on insulater (SGOI)

A production method and uniaxial strain technology, applied in the field of microelectronics, can solve the problems of easily broken silicon wafers, complex process steps, long production cycle, etc., and achieve the effects of low production cost, simple process and reduced production cost.

Inactive Publication Date: 2014-09-24
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The main disadvantages of this technology are: 1) the process steps are complex: the method must undergo thermal oxidation, H + Ion implantation, stripping annealing and other essential processes and related steps
3) Long production cycle: additional thermal oxidation, H + Process steps such as ion implantation and stripping annealing increase the time of its fabrication
4) Low yield: This method is to use two overlapping silicon wafers for mechanical bending and bonding, and to perform high-temperature peeling in the bent state, and the silicon wafers are easily broken

Method used

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  • Manufacturing method of wafer-level uniaxial strain silicon germanium on insulater (SGOI)
  • Manufacturing method of wafer-level uniaxial strain silicon germanium on insulater (SGOI)
  • Manufacturing method of wafer-level uniaxial strain silicon germanium on insulater (SGOI)

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Experimental program
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Effect test

Embodiment 1

[0035] Embodiment 1: Preparation of 4-inch uniaxially strained SGOI wafer

[0036] 1. SGOI wafer selection: 4-inch (100) or (110) wafer ((100) or (110) refers to a certain crystal surface of the SGOI wafer crystal surface), Si substrate thickness 0.4mm, SiO 2 The buried insulating layer is 500nm thick, and the top SiGe layer is 500nm thick.

[0037] SGOI wafer diameter selection: the larger the diameter of the SGOI wafer, the smaller the minimum bending radius of its bending, the greater the strain of the obtained uniaxially strained SGOI wafer, and the final electron migration of the uniaxially strained SGOI wafer The enhancement of rate and hole mobility is also higher. For the SiO-based 2 For uniaxially strained SGOI wafers with buried insulating layers, SGOI wafers with different diameters from 4 inches to 12 inches can be selected according to the different processes of SGOI devices and circuits.

[0038] SGOI wafer crystal plane and crystal direction selection: for t...

Embodiment 2

[0056] Embodiment 2: Preparation of 5-inch uniaxially strained SGOI wafer

[0057] 1. SGOI wafer selection: 5-inch (100) or (110) crystal plane, Si substrate thickness 0.55mm, SiO 2 The buried insulating layer is 300nm thick, and the top SiGe layer is 50nm thick.

[0058] 2. Selection of bending radius of curvature: According to the selected SGOI wafer, the radius of curvature of the bending table is selected to be 0.75m.

[0059] 3. SGOI wafer bending process steps:

[0060] 1) Place the top SiGe layer of the SGOI wafer upwards (or downwards) on a clean stainless steel arc-shaped bending table, and its or direction is parallel to the bending direction, such as image 3 or Figure 4 shown;

[0061] 2) Two cylindrical horizontal pressure bars on the bending table are placed horizontally at both ends of the SGOI wafer, 1 cm away from its edge;

[0062] 3) Rotate the ejector nut of one of the pressure rods on the bending table to fix one end of the SGOI wafer first;

[00...

Embodiment 3

[0071] Embodiment 3: Preparation of 8-inch uniaxially strained SGOI wafer

[0072] 1. SGOI wafer selection: 8-inch (100) or (110) crystal plane, Si substrate thickness 0.68mm, SiO 2 The buried insulating layer is 1000nm thick, and the top SiGe layer is 1000nm thick.

[0073] 2. Selection of bending radius of curvature: According to the selected SGOI wafer, the radius of curvature of the bending table is selected to be 0.5m.

[0074] 3. SGOI wafer bending process steps:

[0075] 1) Place the SiGe layer on the top layer of the SGOI wafer upwards (or downwards) on the arc-shaped bending table, and its bending direction is parallel to the or direction, such as image 3 or Figure 4 shown;

[0076] 2) Two cylindrical horizontal pressure bars on the bending table are placed horizontally at both ends of the SGOI wafer, 1 cm away from its edge;

[0077] 3) Rotate the ejector nut of one of the pressure rods on the bending table to fix one end of the SGOI wafer first;

[0078] 4...

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Abstract

The invention discloses a manufacturing method of wafer-level uniaxial strain silicon germanium on insulater (SGOI). The method comprises the following steps:1) placing a top SiGe layer surface of a SGOI wafer upwards or downwards on an arc bending table; 2) horizontally placing two cylindrical stainless steel compression bars on two ends of the SGOI wafer, wherein there is 1cm between an edge of the SGOI wafer and the two cylindrical stainless steel compression bars; 3) slowly rotating nuts connected with the compression bars so that the SGOI wafer is gradually bended along the arc table board till the SGOI wafer is completely fitted with the arc table board; 4) placing the arc bending table carried with the SGOI wafer in an annealing furnace so as to perform annealing; 5) after the annealing is finished, slowly cooling to a room temperature and taking out the arc bending table carried with the SGOI wafer; 6) rotating the nuts connected with the compression bars so as to rise the compression bars slowly till the bended SGOI wafer returns to an original state. The method has the following advantages that; 1) a technology is simple; 2) making equipment is less; 3) a making temperature scope is large; 4) a yield is high; 5) a strain capacity is high; 6) raw materials are easy to get; 7) making costs are low.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to a semiconductor material manufacturing technology. Specifically, it is a new method of uniaxial strain SGOI (Silicon Germanium On Insulator, silicon germanium on insulating layer) wafer production, which can be used to produce ultra-high-speed, low power consumption, radiation-resistant semiconductor devices and integrated circuits. SGOI wafers can significantly enhance the electron mobility and hole mobility of SGOI wafers, and improve the electrical performance of SGOI devices and circuits. Background technique [0002] Strained SiGe (silicon germanium) has many advantages such as high operating frequency of devices and circuits, low power consumption, cheaper than GaAs, compatibility with Si CMOS technology, and low cost. It is used in microwave devices, mobile communications, high-frequency circuits and other industrial fields It has broad application prospects and com...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/324
Inventor 郝跃王晓晨戴显英金国强李志王琳张鹤鸣
Owner XIDIAN UNIV