Correction apparatus of time series data of receiver and method thereof

Abstract

The invention relates to a correction apparatus of time series data of a receiver and a method thereof. The correction apparatus comprises a clock data recovery (CDR) unit and a weight calculating unit. The CDR unit receives and carries out processing on a compensation signal of an equalization filter so as to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal; the weight calculating unit receives the error signal, the sampling clock signal, the transition sampling signal and the data signal as well as utilizes a run length technology to carry out weight calculation so as to generate weight data; and the weight data are output and a voltage control clock circuit is controlled, so that a phase and frequency of the sampling clock signal are adjusted.

Description

technical field [0001] The present invention relates to a receiver device, in particular to a receiver timing data correction device and method. Background technique [0002] For general communication system architecture, please refer to figure 1 , which includes a transmitter 101, a channel 102, and a receiver equalizer 103, wherein the receiver equalizer 103 includes: an equalization filter 110 and a clock data recovery unit 120 (Clock Data Recovery unit, CDR unit). Wherein, the equalization filter 110 is used for receiving the channel signal VR and compensating it into a compensation signal X, and the CDR unit 120 is used for receiving the compensation signal X and outputting the data signal Z and the sampling clock signal CLK. [0003] The clock data recovery unit 120 in the prior art, when the data changes, ignores the data dependence (data dependent), and adjusts the sampling clock signal CLK faster or slower in the same way, so that the correct CLK may be adjusted in...

AI Technical Summary

Problems solved by technology

Furthermore, when the channel signal VR is severely interfered, the equalization filter 110 cannot fully compensate the channel signal VR, which makes the signal of the compensation signal X incomplete, and the CDR unit 120 receives the incomplete compensation signal X, which will make the CDR unit 120 The phase and frequency of CLK are seriously shifted or out of lock

At this time, when the equalization filter 110 receives the normal channel signal VR to generate the compensation signal X, the CDR unit 120 in the prior art still repeatedly samples the compensation signal X by using the shifted phase and frequency of CLK to obtain Sampling data, and the logical operation unit in the CDR unit 120 uses the sampling data to perform operations, and gradually obtains the phase and frequency of the normal CLK step by step, and cannot be adjusted quickly

However, when the circuit in the CDR unit 120 is disturbed by noise, the CLK is seriously shifted or out of lock, and then when the CDR unit returns to normal, the CDR unit in the prior art cannot quickly adjust the phase and frequency of the CLK. correction and adjustment

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