On-chip multi-core data transmission method and device

A technology of data transmission device and data transmission method, which is applied in the direction of electrical digital data processing, digital computer components, instruments, etc., can solve the problems of limiting and increasing the calculation speed, and achieve the effect of alleviating the increase of network delay and alleviating the negative impact

Inactive Publication Date: 2012-07-11
INST OF COMPUTING TECHNOLOGY - CHINESE ACAD OF SCI +1
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the data transmission method of the traditional on-chip cache has become a bottleneck that limits the improvement of computing speed.

Method used

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  • On-chip multi-core data transmission method and device
  • On-chip multi-core data transmission method and device
  • On-chip multi-core data transmission method and device

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Embodiment Construction

[0056] In order to make the purpose, technical solution and advantages of the present invention clearer, an on-chip data transmission method and device of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0057] In order to improve the memory access bandwidth, the data required by the parallel application of large-scale data transmission should have strong continuity and regularity, which is beneficial for programmers not to schedule data at the storage level. Therefore, the present invention provides programmers with a The programmed on-chip data transmission method enables parallel and large-scale transmission of data between the first-level cache and the second-level cache, and can transmit data between the first-level cache.

[0058] The present...

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Abstract

The invention discloses an on-chip multi-core data transmission method and a device, which is characterized in that the method comprises the following steps: step 1, configuring the data transmission device, generating an instruction stream of the data transmission device by a software interface, and sending the instruction stream to the data transmission device located inside a processor core by the processor core; step 2, receiving the instruction stream by the data transmission device, combining operations of sending the instruction stream to a same SPM (sequential processing machine) or a second level cache, and packaging into a data packet capable of being transmitted on an on-chip network by the data transmission device; step 3, inquiring the on-chip network by a sending module of the data transmission device, and analyzing a data address and giving coordinates of the target SPM or the second level cache; and step 4, receiving data returned by the target SPM or the second level cache or receiving a synchronous signal and returning to a control module by the data transmission device, and returning a signal of finishing the current operation to the processor core by the control module until the number of the returned data or the synchronous signals is equal to the number of the sent requests.

Description

technical field [0001] The invention relates to the field of multi-core processor design, in particular to an on-chip data transmission method and device for a multi-core processor. Background technique [0002] In multi-core processor design, access to storage resources is the main factor restricting performance improvement. Simply increasing the clock frequency and improving the cache strategy can no longer meet the requirements for memory access bandwidth when running large-scale parallel programs. [0003] In traditional multi-core processors, the storage hierarchy is divided into first-level cache, second-level cache, and even multi-level cache and off-chip storage. The L1 cache is generally designed inside the processor core and is directly connected to the memory access module of the processor core. L2 cache and multi-level cache are generally designed to be shared by multiple or all processor cores. The above caches are all on-chip caches and have no independent a...

Claims

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Application Information

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IPC IPC(8): G06F15/173
CPCG06F15/7807G06F15/173
Inventor 张帅焦帅张浩范东睿李海忠
Owner INST OF COMPUTING TECHNOLOGY - CHINESE ACAD OF SCI
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