High-drive current MOSFET

Abstract

A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

Description

technical field [0001] The present invention relates generally to semiconductor devices and, more particularly, to drive current modification in semiconductor devices. Background technique [0002] For nearly a decade, chipmakers have made semiconductor devices faster by miniaturizing them. Also, many techniques for increasing the charge carrier mobility of semiconductor devices have emerged. Stress-line engineering is one aspect that can affect the performance of semiconductor devices to generate high channel currents. In some examples, drive current or channel current can be increased by increasing device scaling or by reducing channel dopants. In addition, the gate dielectric layer can be thinned and the dielectric constant of the gate dielectric layer can be increased. Reducing channel doping to increase drain current typically results in high standby leakage currents that are not suitable for power management. Additionally, thinning the gate dielectric layer and inc...

AI Technical Summary

Problems solved by technology

Reducing channel doping to increase drain current typically results in high standby leakage current that is not suitable for power management

Additionally, thinning the gate dielectric and incorporating high-K dielectric constants increases process complexity and cost

Images