Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method

Abstract

The invention discloses a laminated inverted chip packaging structure of ultra-fine spacing welding plates and a preparation method thereof. According to the embodiment of the invention, the laminated inverted chip packaging structure comprises a substrate, a plurality of vertically-stacked chips and a plurality of conducting columns, wherein a plurality of welding plates are arranged on the substrate; one welding plate is arranged on each chip; and the conducting columns are arranged between the chips and the substrate; a part of the conducting columns are vertically stacked together; and the welding plates on the substrate and the welding plates on the chips are electrically connected through the conducting columns. Bottom filling materials are filled in gaps among the chips and gaps between the chips and the substrate and cover solder on each layer and the conducting columns. With the adoption of the laminated inverted chip packaging structure of the ultra-fine spacing welding plates disclosed by the embodiment of the invention, the requirements on the ultra-fine spacing welding plates on the vertically-stacked chips can be satisfied.

Description

technical field [0001] The invention relates to a stacked flip-chip packaging structure and a manufacturing method, in particular to a stacked flip-chip small-sized thin packaging structure with ultra-fine-pitch pads and a manufacturing method using bottom filling glue. Background technique [0002] Such as figure 1 As shown, in the traditional stacked package structure including two layers of flip chips, the interconnection between the chip pad and the substrate pad is usually the second chip 2 (the chip on the upper side and farther away from the substrate) through a larger The ball-shaped solder bumps are connected to the pads of the substrate 100, and the first chip 1 (the lower chip) is connected to the pads of the substrate through smaller ball-shaped solder bumps. [0003] In order to overcome the problem that solder bumps cannot be applied to ultra-fine-pitch pads in the traditional two-layer flip-chip stacked packaging structure, a conductive pillar interconnection...

AI Technical Summary

Problems solved by technology

The existing chip thinning technology that can realize mass production is generally the thinnest to 30um, so the thickness Tc of the lower chip 1 is at least 30um, resulting in the gap d1 between the lower chip 1 and the substrate 100 being less than 10um

This structure is currently difficult to implement

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