Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof

Abstract

The invention provides a tunneling transistor with a horizontal quasi coaxial cable structure and a forming method thereof. The tunneling transistor comprises a semiconductor substrate, a channel region, a drain region or a source region and a gate structure, wherein the semiconductor substrate has a first doping type; the semiconductor substrate is a source region or a drain region; the channel region is formed on the semiconductor substrate; an insulating layer is formed in the region on the semiconductor substrate, in which the channel region is not formed; the drain region or the source region is formed on the channel region and the insulating layer and has a second doping type; a first part of the channel region is coated by a first part of the drain region or the source region; the gate structure is formed on the first part of the drain region or the source region; and the first part of the drain region or the source region is coated by the gate structure. According to the tunneling transistor provided by the embodiment of the invention, the driving capacity of a TFET (Tunneling Field Effect Transistor) device can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a tunneling transistor with a horizontal quasi-coaxial cable structure and a forming method thereof. Background technique [0002] For a long time, in order to obtain higher chip density, faster working speed and lower power consumption. The feature size of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) has been shrinking continuously following the so-called Moore's law, and their operating speeds are getting faster and faster. At present, it has entered the range of nanoscale. However, a serious challenge that comes with it is the appearance of short-channel effects, such as subthreshold voltage drop (Vt roll-off), drain-induced barrier lowering (DIBL), and source-drain punch through (punch through), etc. , making the off-state leakage current of the device significantly increased, resulting in performance degradation. [0003] At pr...

AI Technical Summary

Problems solved by technology

[0006] The disadvantage of the existing horizontal tunneling TFET device is that: due to the small cross-sectional area of ​​the horizontal tunneling, the driving current is too small, which affects the driving performance of the TFET device

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