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Staggered-pins structure for substrate

A staggered arrangement and pin structure technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problem of not being able to maximize the use of pin space, and achieve the effect of reducing size and high-density packaging.

Active Publication Date: 2012-07-25
SAMSUNG SEMICON CHINA RES & DEV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, existing technologies still cannot maximize the use of space in the pin section

Method used

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  • Staggered-pins structure for substrate
  • Staggered-pins structure for substrate
  • Staggered-pins structure for substrate

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Embodiment Construction

[0027] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the principles employed in the invention.

[0028] It should be appreciated that the dimensions of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, and the present invention is not limited by the illustrated dimensions. In the drawings, the thicknesses of layers, regions, etc., are exaggerated for clarity. The same or similar reference numerals denote the same elements throughout the specification.

[0029] The invention provides a new type of staggered regular hexagonal pins for the substrate, which is used to realize high-density wiring, and at the same time reduce the area o...

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Abstract

The invention discloses a staggered-pins structure for a substrate; in the staggered-pins structure for the substrate, a solder pad arranged on a chip of the substrate is electrically connected with a pin by a bonding lead; the pin is connected to an external circuit through a circuit line, wherein each pin is in regular hexagon shape; a plurality of pins are staggered along an arrangement direction of the solder pad on the chip; according to the staggered-pins structure for the substrate, the space of the pin part can be utilized in maximum so as to realize high-density encapsulation; in addition, the size of an encapsulation piece can be reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, in particular, the invention relates to a staggered pin structure for a substrate of a semiconductor package capable of realizing high-density integration. Background technique [0002] As electronics become smaller, denser and perform better, semiconductors become proportionally smaller as their components and connections become denser. Generally, in order to realize circuit connection, bonding wires are used to connect substrate pins and chip ports through a wire bonding process. The wire bonding process is the use of bonding wires to connect the terminals of an integrated circuit (IC) chip (hereinafter referred to as "pads") to corresponding pins (sometimes referred to as "pads") such as a substrate or printed circuit board (PCB). wire bond pads” or “bond pads”) interconnections are known methods. [0003] Conventional pads for wire bonding are regularly arranged, and the lea...

Claims

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Application Information

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IPC IPC(8): H01L23/49
CPCH01L24/49H01L2224/49433H01L2224/49171H01L2224/05554H01L2224/49H01L2924/14H01L2924/00H01L2924/00012
Inventor 夏一凡
Owner SAMSUNG SEMICON CHINA RES & DEV
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