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Method for managing blocks, memory device and controller thereof

A memory device and controller technology, which is applied in the field of flash memory access, can solve problems such as inability to guarantee processing performance, and achieve the effect of optimal processing performance

Active Publication Date: 2015-06-17
SILICON MOTION INC (CN)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a block management method and related methods for the defect that the management mechanism of the prior art cannot guarantee the best processing performance when performing loss leveling operations in the flash memory. memory device and its controller to solve the above problems

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  • Method for managing blocks, memory device and controller thereof
  • Method for managing blocks, memory device and controller thereof
  • Method for managing blocks, memory device and controller thereof

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Embodiment Construction

[0063] Please refer to figure 1 , figure 1 It is a schematic diagram of a memory device 100 according to a first embodiment of the present invention, wherein the memory device 100 of this embodiment is especially a portable memory device (for example: a memory card conforming to SD / MMC, CF, MS, XD standards ) or solid state drive (SSD, Solid State Drive), etc. The memory device 100 includes: a flash memory (Flash Memory) 120, which includes a plurality of blocks, and the plurality of blocks include at least one information block (Block) 120B; and a controller, used for access (Access) The flash memory 120, wherein the controller is, for example, a memory controller 110. According to this embodiment, the memory controller 110 includes a microprocessor 112 , a read only memory (ROM) 112M, a control logic 114 , at least one buffer memory 116 , and an interface logic 118 . In addition, the ROM 112M of this embodiment is used to store a program code 112C, and the microprocessor ...

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PUM

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Abstract

The invention provides a method for managing blocks. The method is applied to a controller of a flash memory. The flash memory comprises a plurality of blocks. The method comprises the following steps of: selecting a target block with lowest erase frequency in at least part of blocks in a data region of the flash memory to serve as a block to be erased; and determining whether valid data in the target block are moved / copied to a heavily worn block or a lightly worn block according to sequence number of the target block, wherein the sequence numbers of the at least part of blocks respectively correspond to the latest updated sequences of the at least part of blocks; and the wear degree of the heavily worn block is greater than that of the lightly worn block. According to block management achieved by the method, hot data and cold data can be distinguished, and the block with higher wear degree is utilized to store the cold data and the block with lower wear degree is utilized to store the hot data to ensure the best treatment efficiency to be achieved when wear leveling operation is carried out in the flash memory.

Description

technical field [0001] The present invention relates to the access of flash memory (Flash Memory), and more specifically, relates to a method for block management, a related memory device and a controller thereof. Background technique [0002] In recent years, due to the continuous development of flash memory technology, various portable memory devices (for example: memory cards conforming to SD / MMC, CF, MS, XD standards) or solid state drives (Solid State Drive, SSD) with flash memory are widely used implemented in many applications. Therefore, the access control of the flash memory in these memory devices has become a very hot topic. [0003] As far as the commonly used NAND flash memory is concerned, it can be mainly divided into two types of flash memory: single level cell (Single Level Cell, SLC) and multiple level cell (Multiple Level Cell, MLC). Each transistor in the single-level cell flash memory, which is regarded as a memory unit, has only two charge values, whi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/06
Inventor 沈扬智
Owner SILICON MOTION INC (CN)