Manufacturing method of vertical diode array
A diode array and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of reducing the storage performance of PCRAM devices, high sidewall height of shallow trench isolation structures, and affecting the integration of phase change memory cells and the degree of interference immunity, to achieve the effects of improving junction leakage, improving short channel effects, increasing integration and interference immunity
Active Publication Date: 2014-11-26
SEMICON MFG INT (SHANGHAI) CORP
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[0009] The purpose of the present invention is to provide a method for manufacturing a vertical diode array to solve the problem that the high sidewall height of the shallow trench isolation structure in the current preparation process affects the integration degree and interference-free degree of subsequent phase-change memory cells, and reduces the storage capacity of PCRAM devices. performance problem
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[0035] The manufacturing method of the vertical diode array proposed by the present invention will be further described in detail below with reference to the drawings and specific embodiments.
[0036] Such as image 3 As shown, the present invention proposes a method for manufacturing a vertical diode array, which is completed by the steps shown in S301 to S309, combined below image 3 The fabrication process flow diagram shown and Figures 4A-4H The schematic cross-sectional view of the diode array manufacturing process shown in the above-mentioned vertical diode array manufacturing method is described in detail.
[0037] S301, providing a semiconductor substrate, an N / P type region is formed inside the semiconductor substrate, and an epitaxial layer, a first hard mask layer and a second hard mask layer are sequentially formed on the semiconductor substrate.
[0038] Please refer to Figure 4A , providing a semiconductor substrate 400, in which an N / P type region 401 is f...
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The invention relates to the technical field of semiconductor memories, in particular to a manufacturing method of a vertical diode array of a phase-changed random access memory (PCRAM). Photoresist stripping in a word line direction and bit line / word line isolation cleaning operation are carried out after bit line / word line isolation is formed, the side wall of a second oxidation layer remained by bit line / word line isolation is removed, and an STI (Shallow trench isolation) structure, i.e., a memory cell isolation, is etched, so that the side wall of the formed STI structure is lowered, the good insulating property is achieved, a favorable structure of a deep groove in a bit line direction is kept, the length of an N-type or P-type buried layer (NBL or PBL) of a device region is ensured, the good appearance of the vertical diode array is obtained, the following process window property is improved, the short-channel effect and the junction leakage phenomenon are improved, the integration level and the non-disturbance degrees of the following phase-changed memory cells are improved, and the memory property of the PCRAM is lowered.
Description
technical field [0001] The invention relates to the technical field of semiconductor memory, in particular to a method for manufacturing a vertical diode array of a phase-change random access memory. Background technique [0002] Phase change random access memory (PCRAM) is a kind of memory that uses phase change thin film material as storage medium to realize data storage. The reversible phase transition between the crystalline state and the amorphous state can be achieved, and the phase change resistance of different orders of magnitude can be obtained, and the PCRAM device is realized by using the resistance difference when the phase change material transitions between the crystalline state and the amorphous state. non-volatile storage of data. [0003] Currently, PCRAM devices usually include word lines and bit lines perpendicular to each other, and memory cells (phase-change resistors) thereof are electrically coupled between the word lines and the bit lines. In order...
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IPC IPC(8): H01L21/329H01L21/762H01L45/00
Inventor 李凡张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP