Software-hardware co-verification platform

Abstract

The invention discloses a software-hardware co-verification platform, which comprises an upper computer, a virtual in-circuit emulator (ICE), a design under verification (DUV) and a communication part, wherein the virtual ICE communicates with the upper computer through a serial port between servers and is connected with the DUV through programming language interfaces (PLIs); the upper computer is realized on a server equipped with a Linux operating system; and the virtual ICE, the PLI and the DUV are realized on another server equipped with a Linux operating system. The verification environment of the verification platform can be realized only by using the servers with relatively large storage space, so that the problem of limited capacity of a software-hardware co-verification product is solved, and system-level verification of a chip at a design front end can be realized; the prices of the servers are low, so that the cost of integrated product development is reduced; and besides, as the software-hardware co-verification platform is completely realized by using software, a lengthy period of hardware debugging is avoided, the development process of the product is accelerated, and precious time is strived for early listing of the product.

Description

technical field [0001] The invention relates to a software-hardware cooperative verification platform, which is applied to the functional verification of large-scale hardware design at the front-end transfer level (Register Transfer Level, RTL). Background technique [0002] In the process of chip design, verification is a very important link. The full-scan verification of JTAG interface is the most commonly used method in verification. At present, hardware emulators, FPGA and other software and hardware collaborative products have appeared on the market. Although they are easy to develop and implement It has the characteristics of high speed and automatic compilation, but its cost is expensive, often hundreds of thousands or even millions, and there are defects such as long hardware debugging cycle and limited capacity. For the verification of large-scale design, it is impossible to realize the full chip (Full chip) The adequacy and completeness of verification under the mo...

AI Technical Summary

Problems solved by technology

[0002] In the process of chip design, verification is a very important link. The full-scan verification of JTAG interface is the most commonly used method in verification. At present, hardware emulators, FPGA and other software and hardware collaborative products have appeared on the market. Although they are easy to develop and implement It has the characteristics of high speed and automatic compilation, but its cost is expensive, often hundreds of thousands or even millions, and there are defects such as long hardware debugging cycle and limited capacity. For the verification of large-scale design, it is impossible to realize the full chip (Full chip) Sufficiency and completeness of verification under the schema

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