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Method for manufacturing built-in stress nanowire

A nanowire and silicon wafer technology, applied in the field of manufacturing semiconductor nanowires, can solve problems such as stress dislocation and fracture, and achieve the effect of avoiding dislocation

Active Publication Date: 2012-09-19
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Aiming at the problem of dislocation or even fracture caused by stress in the process of manufacturing built-in stress nanowires in the prior art, the present invention provides a method for manufacturing built-in stress silicon nanowires, a method for manufacturing semiconductor devices, and the method Fabricated semiconductor device

Method used

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  • Method for manufacturing built-in stress nanowire
  • Method for manufacturing built-in stress nanowire
  • Method for manufacturing built-in stress nanowire

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0060] step 1

[0061] refer to figure 1 , provide an SOI silicon wafer, the SOI silicon wafer includes a buried oxide layer 1 in the middle and a top silicon layer 2 above the buried oxide layer.

[0062] Deposit a germanium layer or a germanium-silicon layer 3 on the top silicon layer 2, and oxidize the surface of the germanium layer or the germanium-silicon layer by using the germanium-oxygen concentration method. At this time, Ge will concentrate downward into the top silicon layer 2 below, Make the top silicon layer become the top SiGe layer 21, and the top becomes SiO 2 Layer 31, such as figure 2 shown.

[0063] step 2

[0064] Wet removal of SiO 2 Layer 31, on top of the top SiGe layer 21, a layer of silicon layer 4 is epitaxial in sequence (the channel region of SiNWFET will be prepared in this silicon layer, and the channel of SiNWFET will be doped at the same time during the epitaxy process) and a layer of silicon germanium layer 5 ,Such as image 3 shown. ...

Embodiment 2

[0072] step 1

[0073] refer to figure 1 , provide an SOI silicon wafer, the SOI silicon wafer includes a buried oxide layer 1 in the middle and a top silicon layer 2 above the buried oxide layer.

[0074] Deposit a germanium layer or a silicon germanium layer on the top silicon layer 2, and use the germanium oxygen concentration method to oxidize the surface of the germanium layer or the silicon germanium layer. At this time, Ge will concentrate downwards into the top silicon layer 2 below, so that The top silicon layer becomes the top SiGe layer 21 and the uppermost layer becomes SiO 2 Layer 31, such as figure 2 shown.

[0075] step 2

[0076] Wet removal of SiO 2 Layer 31, on top of the top SiGe layer 21, a layer of silicon layer 4 is epitaxial in sequence (the channel region of SiNWFET will be prepared in this silicon layer, and the channel of SiNWFET will be doped at the same time during the epitaxy process) and a layer of silicon germanium layer 5 ,Such as imag...

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Abstract

The invention provides a method for manufacturing a built-in stress nanowire. The method uses a gate-last process (Gate-last), the lateral face of an NWFET area is protected through a SiO2 layer when a grid electrode area is etched, the reverse stress direction borne by the nanowire (SiNW) of the grid electrode area is in the horizontal direction at the time so that the problem that reverse built-in stress of the semiconductor nanowire is not in the horizontal direction is solved, disposition which possibly occurs on the middle portion of the semiconductor nanowire is avoided, even the breaking problem can be solved. The upper surface of a source drain PAD is higher than the SiNW, so that upper surfaces of the source drain and the grid electrode are in a same plane, a grid electrode lateral wall process is not needed, and process flows are simplified.

Description

technical field [0001] The invention relates to a method for manufacturing semiconductor nanowires, in particular to a method for manufacturing built-in stress silicon nanowires, a method for manufacturing semiconductor devices, and the prepared semiconductor devices. Background technique [0002] At present, it is very common to introduce strain engineering in the manufacture of advanced semiconductor devices. For MOSFETs with a channel direction of <110>, when the channel direction has tensile stress, the current driving capability of the NMOSFET can be effectively increased, and when the channel direction has When the compressive stress is applied, the current driving capability of the PMOSFET can be effectively increased. [0003] In the same way, for the most advanced semiconductor nanowire field effect transistor (Nanowire Field Effect Transistor, NWFET), if strain engineering is introduced in the direction of the nanowire length (ie, the channel direction), the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/335B82Y40/00
Inventor 黄晓橹顾经纶
Owner SHANGHAI HUALI MICROELECTRONICS CORP