Method for making semiconductor built-in stress nanowire and semiconductor device
A semiconductor and nanowire technology, applied in the field of semiconductor device production technology, can solve the problem that the reverse built-in stress of semiconductor nanowires is not in the horizontal direction, and achieve the effect of avoiding dislocation
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Embodiment 1
[0061] step 1,
[0062] Such as figure 1 As shown, a semiconductor substrate with a buried oxide layer is provided. Preferably, the substrate is an SOI silicon wafer, including a buried oxide layer 1 and a top semiconductor layer 2 (silicon layer).
[0063] Preferably, the buried oxide layer has a thickness of 10 nm to 1000 nm, and the top semiconductor layer has a thickness of 10 nm to 200 nm.
[0064] The top semiconductor layer 2 originally contains impurity ions, which are used as channel doping ions of the subsequent NWFET.
[0065] step 2
[0066] Such as Figure 2A and Figure 2B As shown, the preparation region of semiconductor nanowire field effect transistor (NanowireFET, NWFET) is determined on the top semiconductor layer 2, and the PR mask 3 is covered on the preparation region of the semiconductor nanowire field effect transistor, and the top semiconductor layer 2 is processed. Photolithography, the top semiconductor layer 2 covered with the PR mask 3 forms ...
Embodiment 2
[0079] step 1,
[0080] Such as figure 1 As shown, a semiconductor substrate with a buried oxide layer is provided. Preferably, the substrate is an SOI silicon wafer, including a buried oxide layer 1 and a top semiconductor layer 2 (silicon layer).
[0081] Preferably, the buried oxide layer has a thickness of 10 nm to 1000 nm, and the top semiconductor layer has a thickness of 10 nm to 200 nm.
[0082] Ion implantation is performed in the top semiconductor layer 2 to include impurity ions as channel dopant ions of the subsequent NWFET.
[0083] step 2
[0084] Determine the preparation area of the semiconductor nanowire field effect transistor (NanowireFET, NWFET) on the top semiconductor layer 2, cover the hard mask on the preparation area of the semiconductor nanowire field effect transistor, etch the top semiconductor layer 2, cover The top semiconductor layer 2 with a hard mask forms the preparation area of the semiconductor nanowire field effect transistor, the...
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Abstract
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